Commit 23de60e6 authored by oharboe's avatar oharboe
Browse files

Michael Bruck <mbruck@digenius.de> ARM11 various updates + fix formatting.

git-svn-id: svn://svn.berlios.de/openocd/trunk@1512 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent a247833a
......@@ -53,6 +53,8 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11);
bool arm11_config_memwrite_burst = true;
bool arm11_config_memwrite_error_fatal = true;
u32 arm11_vcr = 0;
bool arm11_config_memrw_no_increment = false;
bool arm11_config_step_irq_enable = false;
#define ARM11_HANDLER(x) \
.x = arm11_##x
......@@ -383,9 +385,9 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
{
arm11_add_debug_SCAN_N(arm11, 0x05, TAP_INVALID);
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
scan_field_t chain5_fields[3];
......@@ -422,7 +424,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
while (1)
{
/* MRC p14,0,R0,c5,c10,0 */
// arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
// arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
/* mcr 15, 0, r0, cr7, cr10, {4} */
arm11_run_instr_no_data1(arm11, 0xee070f9a);
......@@ -562,14 +564,13 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
/* MRC p14,0,r?,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
// LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
// LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
}}
arm11_run_instr_data_finish(arm11);
/* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */
{
u32 DSCR = arm11_read_DSCR(arm11);
......@@ -614,9 +615,9 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
{
arm11_add_debug_SCAN_N(arm11, 0x05, TAP_INVALID);
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
scan_field_t chain5_fields[3];
......@@ -774,8 +775,8 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
FNC_INFO;
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
arm11_common_t * arm11 = target->arch_info;
......@@ -862,6 +863,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
{
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
{
return retval;
......@@ -954,6 +956,13 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
/* resume */
if (arm11_config_step_irq_enable)
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
else
R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
arm11_leave_debug_state(arm11);
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
......@@ -983,9 +992,13 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
/* save state */
arm11_on_enter_debug_state(arm11);
/* restore default state */
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
}
// target->state = TARGET_HALTED;
// target->state = TARGET_HALTED;
target->debug_reason = DBG_REASON_SINGLESTEP;
if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
......@@ -1082,9 +1095,9 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
}
/* target memory access
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size>
*/
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size>
*/
int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
{
/** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
......@@ -1116,7 +1129,9 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
for (i = 0; i < count; i++)
{
/* ldrb r1, [r0], #1 */
arm11_run_instr_no_data1(arm11, 0xe4d01001);
/* ldrb r1, [r0] */
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
u32 res;
/* MCR p14,0,R1,c0,c5,0 */
......@@ -1137,7 +1152,8 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
for (i = 0; i < count; i++)
{
/* ldrh r1, [r0], #2 */
arm11_run_instr_no_data1(arm11, 0xe0d010b2);
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
u32 res;
......@@ -1153,7 +1169,10 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
case 4:
/* LDC p14,c5,[R0],#4 */
arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
/* LDC p14,c5,[R0] */
arm11_run_instr_data_from_core(arm11,
(!arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00),
(u32 *)buffer, count);
break;
}
......@@ -1194,7 +1213,9 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
/* strb r1, [r0], #1 */
arm11_run_instr_no_data1(arm11, 0xe4c01001);
/* strb r1, [r0] */
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
}}
break;
......@@ -1213,7 +1234,9 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
/* strh r1, [r0], #2 */
arm11_run_instr_no_data1(arm11, 0xe0c010b2);
/* strh r1, [r0] */
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
}}
break;
......@@ -1225,12 +1248,18 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
if (!arm11_config_memwrite_burst)
{
/* STC p14,c5,[R0],#4 */
arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
/* STC p14,c5,[R0]*/
arm11_run_instr_data_to_core(arm11,
(!arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00),
(u32 *)buffer, count);
}
else
{
/* STC p14,c5,[R0],#4 */
arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
/* STC p14,c5,[R0]*/
arm11_run_instr_data_to_core_noack(arm11,
(!arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00),
(u32 *)buffer, count);
}
break;
......@@ -1238,6 +1267,7 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
#if 1
/* r0 verification */
if (!arm11_config_memrw_no_increment)
{
u32 r0;
......@@ -1552,7 +1582,6 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target
{
/* Initialize anything we can set up without talking to the target */
return arm11_build_reg_cache(target);
}
/* talk to the target and set things up */
......@@ -1565,7 +1594,7 @@ int arm11_examine(struct target_s *target)
/* check IDCODE */
arm11_add_IR(arm11, ARM11_IDCODE, TAP_INVALID);
arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
scan_field_t idcode_field;
......@@ -1575,9 +1604,9 @@ int arm11_examine(struct target_s *target)
/* check DIDR */
arm11_add_debug_SCAN_N(arm11, 0x00, TAP_INVALID);
arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
scan_field_t chain0_fields[2];
......@@ -1611,7 +1640,6 @@ int arm11_examine(struct target_s *target)
return ERROR_FAIL;
}
arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
......@@ -1740,6 +1768,7 @@ int arm11_build_reg_cache(target_t *target)
rs->def_index = i;
rs->target = target;
}
return ERROR_OK;
}
......@@ -1799,6 +1828,8 @@ int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char
BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
......@@ -1830,22 +1861,24 @@ const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode
arm11_common_t * arm11_find_target(const char * arg)
{
jtag_tap_t *tap;
jtag_tap_t * tap;
target_t * t;
tap = jtag_TapByString( arg );
if( !tap ){
return NULL;
}
tap = jtag_TapByString(arg);
for (t = all_targets; t; t = t->next){
if( t->tap == tap ){
if( 0 == strcmp(t->type->name,"arm11")){
arm11_common_t * arm11 = t->arch_info;
return arm11;
}
}
if (!tap)
return 0;
for (t = all_targets; t; t = t->next)
{
if (t->tap != tap)
continue;
/* if (t->type == arm11_target) */
if (0 == strcmp(t->type->name, "arm11"))
return t->arch_info;
}
return 0;
}
......@@ -1865,7 +1898,6 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
read ? arm11_mrc_syntax : arm11_mcr_syntax);
return -1;
}
if (arm11->target->state != TARGET_HALTED)
......@@ -1949,11 +1981,16 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
memwrite_burst)
RC_FINAL_BOOL( "error_fatal",
"Terminate program if transfer error was found (default: enabled)",
RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)",
memwrite_error_fatal)
)
RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
memrw_no_increment)
RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
step_irq_enable)
RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
arm11_handle_vcr)
......
......@@ -48,6 +48,9 @@
23 * ARM11_REGCACHE_MODEREGS + \
9 * ARM11_REGCACHE_FREGS)
#define ARM11_TAP_DEFAULT TAP_INVALID
typedef struct arm11_register_history_s
{
u32 value;
......@@ -64,9 +67,9 @@ enum arm11_debug_version
typedef struct arm11_common_s
{
target_t * target;
target_t * target; /**< Reference back to the owner */
arm_jtag_t jtag_info;
arm_jtag_t jtag_info; /**< Handler to access assigned JTAG device */
/** \name Processor type detection */
/*@{*/
......@@ -83,11 +86,13 @@ typedef struct arm11_common_s
/*@}*/
u32 last_dscr; /**< Last retrieved DSCR value;
* Can be used to detect changes */
Use only for debug message generation */
bool trst_active;
bool halt_requested;
bool simulate_reset_on_next_halt;
bool halt_requested; /**< Keep track if arm11_halt() calls occured
during reset. Otherwise do it ASAP. */
bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
/** \name Shadow registers to save processor state */
/*@{*/
......@@ -140,6 +145,7 @@ enum arm11_dscr
ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
ARM11_DSCR_MODE_SELECT = 1 << 14,
ARM11_DSCR_WDTR_FULL = 1 << 29,
......
......@@ -95,7 +95,7 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo
*
* \param arm11 Target state variable.
* \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
* \param state Pass the final TAP state or TAP_INVALID for the default value (Pause-IR).
* \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR).
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
......@@ -103,13 +103,9 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
{
jtag_tap_t *tap;
tap = arm11->jtag_info.tap;
if( tap == NULL ){
/* FIX!!!! error is logged, but not propagated back up the call stack... */
LOG_ERROR( "tap is null here! This is bad!");
return;
}
if (buf_get_u32(tap->cur_instr, 0, 5) == instr){
if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
{
JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
return;
}
......@@ -120,7 +116,7 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
arm11_setup_field(arm11, 5, &instr, NULL, &field);
arm11_add_ir_scan_vc(1, &field, state == TAP_INVALID ? TAP_IRPAUSE : state);
arm11_add_ir_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state);
}
/** Verify shifted out data from Scan Chain Register (SCREG)
......@@ -152,17 +148,17 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s
*
* \param arm11 Target state variable.
* \param chain Scan chain that will be selected.
* \param state Pass the final TAP state or TAP_INVALID for the default
* \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
* value (Pause-DR).
*
* The chain takes effect when Update-DR is passed (usually when subsequently
* the INTEXT/EXTEST instructions are written).
*
* \warning (Obsolete) Using this twice in a row will \em fail. The first call will end
* in Pause-DR. The second call, due to the IR caching, will not
* go through Capture-DR when shifting in the new scan chain number.
* As a result the verification in arm11_in_handler_SCAN_N() must
* fail.
* \warning (Obsolete) Using this twice in a row will \em fail. The first
* call will end in Pause-DR. The second call, due to the IR
* caching, will not go through Capture-DR when shifting in the
* new scan chain number. As a result the verification in
* arm11_in_handler_SCAN_N() must fail.
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
......@@ -171,7 +167,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
{
JTAG_DEBUG("SCREG <= 0x%02x", chain);
arm11_add_IR(arm11, ARM11_SCAN_N, TAP_INVALID);
arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
scan_field_t field;
......@@ -179,7 +175,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
field.in_handler = arm11_in_handler_SCAN_N;
arm11_add_dr_scan_vc(1, &field, state == TAP_INVALID ? TAP_DRPAUSE : state);
arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
}
/** Write an instruction into the ITR register
......@@ -188,7 +184,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
* \param inst An ARM11 processor instruction/opcode.
* \param flag Optional parameter to retrieve the InstCompl flag
* (this will be written when the JTAG chain is executed).
* \param state Pass the final TAP state or TAP_INVALID for the default
* \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
* value (Run-Test/Idle).
*
* \remarks By default this ends with Run-Test/Idle state
......@@ -208,7 +204,7 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state
arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
arm11_add_dr_scan_vc(asizeof(itr), itr, state == TAP_INVALID ? TAP_IDLE : state);
arm11_add_dr_scan_vc(asizeof(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state);
}
/** Read the Debug Status and Control Register (DSCR)
......@@ -222,9 +218,9 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state
*/
u32 arm11_read_DSCR(arm11_common_t * arm11)
{
arm11_add_debug_SCAN_N(arm11, 0x01, TAP_INVALID);
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
u32 dscr;
scan_field_t chain1_field;
......@@ -254,9 +250,9 @@ u32 arm11_read_DSCR(arm11_common_t * arm11)
*/
void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
{
arm11_add_debug_SCAN_N(arm11, 0x01, TAP_INVALID);
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
scan_field_t chain1_field;
......@@ -331,7 +327,7 @@ enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
*/
void arm11_run_instr_data_prepare(arm11_common_t * arm11)
{
arm11_add_debug_SCAN_N(arm11, 0x05, TAP_INVALID);
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
}
/** Cleanup after ITR/DTR operations
......@@ -350,7 +346,7 @@ void arm11_run_instr_data_prepare(arm11_common_t * arm11)
*/
void arm11_run_instr_data_finish(arm11_common_t * arm11)
{
arm11_add_debug_SCAN_N(arm11, 0x00, TAP_INVALID);
arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
}
......@@ -365,7 +361,7 @@ void arm11_run_instr_data_finish(arm11_common_t * arm11)
*/
void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, TAP_INVALID);
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
while (count--)
{
......@@ -414,11 +410,11 @@ void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
*/
void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, TAP_INVALID);
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
scan_field_t chain5_fields[3];
......@@ -446,7 +442,7 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data
data++;
}
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
do
{
......@@ -495,11 +491,11 @@ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
*/
void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, TAP_INVALID);
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
scan_field_t chain5_fields[3];
......@@ -527,7 +523,7 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32
}
}
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
chain5_fields[0].out_value = 0;
chain5_fields[1].in_value = ReadyPos++;
......@@ -584,11 +580,11 @@ void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
*/
void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, TAP_INVALID);
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
scan_field_t chain5_fields[3];
......@@ -666,9 +662,9 @@ void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32
*/
void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
{
arm11_add_debug_SCAN_N(arm11, 0x07, TAP_INVALID);
arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
scan_field_t chain7_fields[3];
......
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