Commit 23de60e6 authored by oharboe's avatar oharboe
Browse files

Michael Bruck <mbruck@digenius.de> ARM11 various updates + fix formatting.

git-svn-id: svn://svn.berlios.de/openocd/trunk@1512 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent a247833a
......@@ -50,9 +50,11 @@
static void arm11_on_enter_debug_state(arm11_common_t * arm11);
bool arm11_config_memwrite_burst = true;
bool arm11_config_memwrite_error_fatal = true;
u32 arm11_vcr = 0;
bool arm11_config_memwrite_burst = true;
bool arm11_config_memwrite_error_fatal = true;
u32 arm11_vcr = 0;
bool arm11_config_memrw_no_increment = false;
bool arm11_config_step_irq_enable = false;
#define ARM11_HANDLER(x) \
.x = arm11_##x
......@@ -131,9 +133,9 @@ enum arm11_regtype
typedef struct arm11_reg_defs_s
{
char * name;
u32 num;
int gdb_num;
char * name;
u32 num;
int gdb_num;
enum arm11_regtype type;
} arm11_reg_defs_t;
......@@ -308,8 +310,8 @@ reg_t arm11_gdb_dummy_fps_reg =
*
* \param arm11 Target state variable.
* \param dscr If the current DSCR content is
* available a pointer to a word holding the
* DSCR can be passed. Otherwise use NULL.
* available a pointer to a word holding the
* DSCR can be passed. Otherwise use NULL.
*/
void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
{
......@@ -319,37 +321,37 @@ void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
if (!dscr)
{
dscr = &dscr_local_tmp_copy;
*dscr = arm11_read_DSCR(arm11);
dscr = &dscr_local_tmp_copy;
*dscr = arm11_read_DSCR(arm11);
}
if (!(*dscr & ARM11_DSCR_MODE_SELECT))
{
LOG_DEBUG("Bringing target into debug mode");
LOG_DEBUG("Bringing target into debug mode");
*dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
arm11_write_DSCR(arm11, *dscr);
*dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
arm11_write_DSCR(arm11, *dscr);
/* add further reset initialization here */
/* add further reset initialization here */
arm11->simulate_reset_on_next_halt = true;
arm11->simulate_reset_on_next_halt = true;
if (*dscr & ARM11_DSCR_CORE_HALTED)
{
/** \todo TODO: this needs further scrutiny because
* arm11_on_enter_debug_state() never gets properly called
*/
if (*dscr & ARM11_DSCR_CORE_HALTED)
{
/** \todo TODO: this needs further scrutiny because
* arm11_on_enter_debug_state() never gets properly called
*/
arm11->target->state = TARGET_HALTED;
arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
}
else
{
arm11->target->state = TARGET_RUNNING;
arm11->target->debug_reason = DBG_REASON_NOTHALTED;
}
arm11->target->state = TARGET_HALTED;
arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
}
else
{
arm11->target->state = TARGET_RUNNING;
arm11->target->debug_reason = DBG_REASON_NOTHALTED;
}
arm11_sc7_clear_vbw(arm11);
arm11_sc7_clear_vbw(arm11);
}
}
......@@ -371,8 +373,8 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
{size_t i;
for(i = 0; i < asizeof(arm11->reg_values); i++)
{
arm11->reg_list[i].valid = 1;
arm11->reg_list[i].dirty = 0;
arm11->reg_list[i].valid = 1;
arm11->reg_list[i].dirty = 0;
}}
/* Save DSCR */
......@@ -383,21 +385,21 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
{
arm11_add_debug_SCAN_N(arm11, 0x05, TAP_INVALID);
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
scan_field_t chain5_fields[3];
scan_field_t chain5_fields[3];
arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
else
{
arm11->reg_list[ARM11_RC_WDTR].valid = 0;
arm11->reg_list[ARM11_RC_WDTR].valid = 0;
}
......@@ -413,34 +415,34 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
/* From the spec:
Before executing any instruction in debug state you have to drain the write buffer.
This ensures that no imprecise Data Aborts can return at a later point:*/
Before executing any instruction in debug state you have to drain the write buffer.
This ensures that no imprecise Data Aborts can return at a later point:*/
/** \todo TODO: Test drain write buffer. */
#if 0
while (1)
{
/* MRC p14,0,R0,c5,c10,0 */
// arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
/* MRC p14,0,R0,c5,c10,0 */
// arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
/* mcr 15, 0, r0, cr7, cr10, {4} */
arm11_run_instr_no_data1(arm11, 0xee070f9a);
/* mcr 15, 0, r0, cr7, cr10, {4} */
arm11_run_instr_no_data1(arm11, 0xee070f9a);
u32 dscr = arm11_read_DSCR(arm11);
u32 dscr = arm11_read_DSCR(arm11);
LOG_DEBUG("DRAIN, DSCR %08x", dscr);
LOG_DEBUG("DRAIN, DSCR %08x", dscr);
if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
{
arm11_run_instr_no_data1(arm11, 0xe320f000);
if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
{
arm11_run_instr_no_data1(arm11, 0xe320f000);
dscr = arm11_read_DSCR(arm11);
dscr = arm11_read_DSCR(arm11);
LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
break;
}
break;
}
}
#endif
......@@ -453,8 +455,8 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
{size_t i;
for (i = 0; i < 15; i++)
{
/* MCR p14,0,R?,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
/* MCR p14,0,R?,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
}}
/* save rDTR */
......@@ -463,12 +465,12 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
{
/* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
/* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
}
else
{
arm11->reg_list[ARM11_RC_RDTR].valid = 0;
arm11->reg_list[ARM11_RC_RDTR].valid = 0;
}
/* save CPSR */
......@@ -485,27 +487,27 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
if (R(CPSR) & ARM11_CPSR_J) /* Java state */
{
arm11->reg_values[ARM11_RC_PC] -= 0;
arm11->reg_values[ARM11_RC_PC] -= 0;
}
else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
{
arm11->reg_values[ARM11_RC_PC] -= 4;
arm11->reg_values[ARM11_RC_PC] -= 4;
}
else /* ARM state */
{
arm11->reg_values[ARM11_RC_PC] -= 8;
arm11->reg_values[ARM11_RC_PC] -= 8;
}
if (arm11->simulate_reset_on_next_halt)
{
arm11->simulate_reset_on_next_halt = false;
arm11->simulate_reset_on_next_halt = false;
LOG_DEBUG("Reset c1 Control Register");
LOG_DEBUG("Reset c1 Control Register");
/* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
/* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
/* MCR p15,0,R0,c1,c0,0 */
arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
/* MCR p15,0,R0,c1,c0,0 */
arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
}
......@@ -519,23 +521,23 @@ void arm11_dump_reg_changes(arm11_common_t * arm11)
{size_t i;
for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
if (!arm11->reg_list[i].valid)
{
if (arm11->reg_history[i].valid)
LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
}
else
{
if (arm11->reg_history[i].valid)
if (!arm11->reg_list[i].valid)
{
if (arm11->reg_history[i].value != arm11->reg_values[i])
LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
if (arm11->reg_history[i].valid)
LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
}
else
{
LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
if (arm11->reg_history[i].valid)
{
if (arm11->reg_history[i].value != arm11->reg_values[i])
LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
}
else
{
LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
}
}
}
}}
}
......@@ -556,27 +558,26 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
{size_t i;
for (i = 1; i < 15; i++)
{
if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
continue;
if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
continue;
/* MRC p14,0,r?,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
/* MRC p14,0,r?,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
// LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
// LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
}}
arm11_run_instr_data_finish(arm11);
/* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */
{
u32 DSCR = arm11_read_DSCR(arm11);
u32 DSCR = arm11_read_DSCR(arm11);
if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
}
if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
}
}
arm11_run_instr_data_prepare(arm11);
......@@ -585,8 +586,8 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
{
/* MCR p14,0,R0,c0,c5,0 */
arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
/* MCR p14,0,R0,c0,c5,0 */
arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
}
/* restore CPSR */
......@@ -614,20 +615,20 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
{
arm11_add_debug_SCAN_N(arm11, 0x05, TAP_INVALID);
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID);
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
scan_field_t chain5_fields[3];
scan_field_t chain5_fields[3];
u8 Ready = 0; /* ignored */
u8 Valid = 0; /* ignored */
u8 Ready = 0; /* ignored */
u8 Valid = 0; /* ignored */
arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
arm11_record_register_history(arm11);
......@@ -638,11 +639,11 @@ void arm11_record_register_history(arm11_common_t * arm11)
{size_t i;
for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
arm11->reg_history[i].value = arm11->reg_values[i];
arm11->reg_history[i].valid = arm11->reg_list[i].valid;
arm11->reg_history[i].value = arm11->reg_values[i];
arm11->reg_history[i].valid = arm11->reg_list[i].valid;
arm11->reg_list[i].valid = 0;
arm11->reg_list[i].dirty = 0;
arm11->reg_list[i].valid = 0;
arm11->reg_list[i].dirty = 0;
}}
}
......@@ -655,7 +656,7 @@ int arm11_poll(struct target_s *target)
arm11_common_t * arm11 = target->arch_info;
if (arm11->trst_active)
return ERROR_OK;
return ERROR_OK;
u32 dscr = arm11_read_DSCR(arm11);
......@@ -665,27 +666,27 @@ int arm11_poll(struct target_s *target)
if (dscr & ARM11_DSCR_CORE_HALTED)
{
if (target->state != TARGET_HALTED)
{
enum target_state old_state = target->state;
if (target->state != TARGET_HALTED)
{
enum target_state old_state = target->state;
LOG_DEBUG("enter TARGET_HALTED");
target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
arm11_on_enter_debug_state(arm11);
LOG_DEBUG("enter TARGET_HALTED");
target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
arm11_on_enter_debug_state(arm11);
target_call_event_callbacks(target,
old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
}
target_call_event_callbacks(target,
old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
}
}
else
{
if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
{
LOG_DEBUG("enter TARGET_RUNNING");
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
}
if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
{
LOG_DEBUG("enter TARGET_RUNNING");
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
}
}
return ERROR_OK;
......@@ -716,11 +717,11 @@ int arm11_halt(struct target_s *target)
arm11_common_t * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
if (target->state == TARGET_UNKNOWN)
{
arm11->simulate_reset_on_next_halt = true;
arm11->simulate_reset_on_next_halt = true;
}
if (target->state == TARGET_HALTED)
......@@ -731,8 +732,8 @@ int arm11_halt(struct target_s *target)
if (arm11->trst_active)
{
arm11->halt_requested = true;
return ERROR_OK;
arm11->halt_requested = true;
return ERROR_OK;
}
arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
......@@ -746,10 +747,10 @@ int arm11_halt(struct target_s *target)
while (1)
{
dscr = arm11_read_DSCR(arm11);
dscr = arm11_read_DSCR(arm11);
if (dscr & ARM11_DSCR_CORE_HALTED)
break;
if (dscr & ARM11_DSCR_CORE_HALTED)
break;
}
arm11_on_enter_debug_state(arm11);
......@@ -760,7 +761,7 @@ int arm11_halt(struct target_s *target)
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
if((retval = target_call_event_callbacks(target,
old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
{
return retval;
}
......@@ -773,14 +774,14 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
int retval = ERROR_OK;
FNC_INFO;
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
arm11_common_t * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
if (target->state != TARGET_HALTED)
......@@ -790,7 +791,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
}
if (!current)
R(PC) = address;
R(PC) = address;
LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
......@@ -800,43 +801,43 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
/* Set up breakpoints */
if (!debug_execution)
{
/* check if one matches PC and step over it if necessary */
/* check if one matches PC and step over it if necessary */
breakpoint_t * bp;
breakpoint_t * bp;
for (bp = target->breakpoints; bp; bp = bp->next)
{
if (bp->address == R(PC))
for (bp = target->breakpoints; bp; bp = bp->next)
{
LOG_DEBUG("must step over %08x", bp->address);
arm11_step(target, 1, 0, 0);
break;
if (bp->address == R(PC))
{
LOG_DEBUG("must step over %08x", bp->address);
arm11_step(target, 1, 0, 0);
break;
}
}
}
/* set all breakpoints */
/* set all breakpoints */
size_t brp_num = 0;
size_t brp_num = 0;
for (bp = target->breakpoints; bp; bp = bp->next)
{
arm11_sc7_action_t brp[2];
for (bp = target->breakpoints; bp; bp = bp->next)
{
arm11_sc7_action_t brp[2];
brp[0].write = 1;
brp[0].address = ARM11_SC7_BVR0 + brp_num;
brp[0].value = bp->address;
brp[1].write = 1;
brp[1].address = ARM11_SC7_BCR0 + brp_num;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
brp[0].write = 1;
brp[0].address = ARM11_SC7_BVR0 + brp_num;
brp[0].value = bp->address;
brp[1].write = 1;
brp[1].address = ARM11_SC7_BCR0 + brp_num;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
arm11_sc7_run(arm11, brp, asizeof(brp));
arm11_sc7_run(arm11, brp, asizeof(brp));
LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
brp_num++;
}
brp_num++;
}
arm11_sc7_set_vcr(arm11, arm11_vcr);
arm11_sc7_set_vcr(arm11, arm11_vcr);
}
arm11_leave_debug_state(arm11);
......@@ -850,18 +851,19 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
while (1)
{
u32 dscr = arm11_read_DSCR(arm11);
u32 dscr = arm11_read_DSCR(arm11);
LOG_DEBUG("DSCR %08x", dscr);
LOG_DEBUG("DSCR %08x", dscr);
if (dscr & ARM11_DSCR_CORE_RESTARTED)
break;
if (dscr & ARM11_DSCR_CORE_RESTARTED)
break;
}
if (!debug_execution)
{
target->state = TARGET_RUNNING;
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
{
return retval;
......@@ -869,7 +871,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
}
else
{
target->state = TARGET_DEBUG_RUNNING;
target->state = TARGET_DEBUG_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
{
......@@ -887,18 +889,18 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
FNC_INFO;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
arm11_common_t * arm11 = target->arch_info;
if (!current)
R(PC) = address;
R(PC) = address;
LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
......@@ -911,81 +913,92 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070)