Commit 18293612 authored by oharboe's avatar oharboe
Browse files

define resetting the target into the halted or running

state as an atomic operation.

git-svn-id: svn://svn.berlios.de/openocd/trunk@888 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 3a489618
......@@ -995,6 +995,13 @@ int arm11_assert_reset(struct target_s *target)
arm11->trst_active = true;
#endif
if (target->reset_halt)
{
int retval;
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
}
return ERROR_OK;
}
......
......@@ -815,6 +815,12 @@ int arm7_9_assert_reset(target_t *target)
armv4_5_invalidate_core_regs(target);
if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
{
/* debug entry was already prepared in arm7_9_assert_reset() */
target->debug_reason = DBG_REASON_DBGRQ;
}
return ERROR_OK;
}
......@@ -832,13 +838,6 @@ int arm7_9_deassert_reset(target_t *target)
/* set up embedded ice registers again */
if ((retval=target->type->examine(target))!=ERROR_OK)
return retval;
if (target->reset_halt)
{
/* halt the CPU as embedded ice was not set up in reset */
if ((retval=target->type->halt(target))!=ERROR_OK)
return retval;
}
}
return retval;
}
......@@ -975,9 +974,9 @@ int arm7_9_soft_reset_halt(struct target_s *target)
int arm7_9_halt(target_t *target)
{
if ((target->state==TARGET_RESET)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)!=0))
if (target->state==TARGET_RESET)
{
LOG_WARNING("arm7/9 can't halt a target in reset if srst pulls trst - halting after reset");
LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
return ERROR_OK;
}
......@@ -998,24 +997,6 @@ int arm7_9_halt(target_t *target)
LOG_WARNING("target was in unknown state when halt was requested");
}
if (target->state == TARGET_RESET)
{
if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
{
LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
return ERROR_TARGET_FAILURE;
}
else
{
/* we came here in a reset_halt or reset_init sequence
* debug entry was already prepared in arm7_9_assert_reset()
*/
target->debug_reason = DBG_REASON_DBGRQ;
return ERROR_OK;
}
}
if (arm7_9->use_dbgrq)
{
/* program EmbeddedICE Debug Control Register to assert DBGRQ
......
......@@ -762,6 +762,13 @@ int cortex_m3_assert_reset(target_t *target)
armv7m_invalidate_core_regs(target);
if (target->reset_halt)
{
int retval;
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
}
return ERROR_OK;
}
......
......@@ -266,6 +266,14 @@ int mips_m4k_assert_reset(target_t *target)
mips32_invalidate_core_regs(target);
if (target->reset_halt)
{
int retval;
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
}
return ERROR_OK;
}
......
......@@ -308,18 +308,6 @@ int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mo
target = target->next;
}
/* request target halt if necessary, and schedule further action */
target = targets;
while (target)
{
if (reset_mode!=RESET_RUN)
{
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
}
target = target->next;
}
target = targets;
while (target)
{
......
......@@ -1579,6 +1579,13 @@ int xscale_assert_reset(target_t *target)
jtag_execute_queue();
target->state = TARGET_RESET;
if (target->reset_halt)
{
int retval;
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
}
return ERROR_OK;
}
......
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