Commit 0fe2a543 authored by ntfreak's avatar ntfreak
Browse files

- 16 and 32 bit unaligned accesses supported

- uses packed transfers for 8/16bit read/writes greater than 4bytes
- 8/16bit transfers now use address auto increment


git-svn-id: svn://svn.berlios.de/openocd/trunk@495 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 09e303bb
......@@ -111,10 +111,10 @@ armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
/* CORE_SP are accesible using MSR and MRS instructions */
#if 0
// {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
// {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
// {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
// {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
{0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
{0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
{0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
{0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
#endif
{0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
......
......@@ -85,46 +85,17 @@ typedef struct armv7m_common_s
enum armv7m_mode core_mode;
enum armv7m_state core_state;
int exception_number;
int (*full_context)(struct target_s *target);
/* Direct processor core register read and writes */
int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value);
/* register cache to processor synchronization */
int (*read_core_reg)(struct target_s *target, int num);
int (*write_core_reg)(struct target_s *target, int num);
/* get or set register through cache, return error if target is running and synchronisation is impossible */
int (*get_core_reg_32)(struct target_s *target, int num, u32* value);
int (*set_core_reg_32)(struct target_s *target, int num, u32 value);
arm_jtag_t jtag_info;
reg_cache_t *eice_cache;
reg_cache_t *etm_cache;
int (*examine_debug_reason)(target_t *target);
void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
/*
void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
*/
/*
void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
void (*load_word_regs)(target_t *target, u32 mask);
void (*load_hword_reg)(target_t *target, int num);
void (*load_byte_reg)(target_t *target, int num);
void (*store_word_regs)(target_t *target, u32 mask);
void (*store_hword_reg)(target_t *target, int num);
void (*store_byte_reg)(target_t *target, int num);
void (*write_pc)(target_t *target, u32 pc);
void (*branch_resume)(target_t *target);
*/
void (*pre_debug_entry)(target_t *target);
void (*post_debug_entry)(target_t *target);
......
......@@ -144,6 +144,7 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval
return retvalue;
}
#if 0
/* Enable interrupts */
int cortex_m3_cpsie(target_t *target, u32 IF)
{
......@@ -155,6 +156,7 @@ int cortex_m3_cpsid(target_t *target, u32 IF)
{
return cortex_m3_exec_opcode(target, ARMV7M_T_CPSID(IF), 2);
}
#endif
int cortex_m3_endreset_event(target_t *target)
{
......@@ -325,7 +327,6 @@ int cortex_m3_debug_entry(target_t *target)
cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
}
/* Now we can load SP core registers */
for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++)
{
......@@ -1212,39 +1213,31 @@ int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 co
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
int retval;
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
return ERROR_INVALID_ARGUMENTS;
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
/* Is not optimal, autoincrement of tar should be used ( ahbap_block_read and CSW_ADDRINC_SINGLE ) */
/* cortex_m3 handles unaligned memory access */
switch (size)
{
case 4:
/* TODOLATER Check error return value ! */
{
ahbap_read_buf(swjdp, buffer, 4 * count, address);
}
retval = ahbap_read_buf_u32(swjdp, buffer, 4 * count, address);
break;
case 2:
{
ahbap_read_buf_u16(swjdp, buffer, 2 * count, address);
}
retval = ahbap_read_buf_u16(swjdp, buffer, 2 * count, address);
break;
case 1:
{
ahbap_read_buf(swjdp, buffer, count, address);
}
retval = ahbap_read_buf_u8(swjdp, buffer, count, address);
break;
default:
ERROR("BUG: we shouldn't get here");
exit(-1);
}
return ERROR_OK;
return retval;
}
int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
......@@ -1253,45 +1246,34 @@ int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 c
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
int retval;
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
return ERROR_INVALID_ARGUMENTS;
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
switch (size)
{
case 4:
/* TODOLATER Check error return value ! */
{
ahbap_write_buf(swjdp, buffer, 4 * count, address);
}
retval = ahbap_write_buf_u32(swjdp, buffer, 4 * count, address);
break;
case 2:
{
ahbap_write_buf_u16(swjdp, buffer, 2 * count, address);
}
retval = ahbap_write_buf_u16(swjdp, buffer, 2 * count, address);
break;
case 1:
{
ahbap_write_buf(swjdp, buffer, count, address);
}
retval = ahbap_write_buf_u8(swjdp, buffer, count, address);
break;
default:
ERROR("BUG: we shouldn't get here");
exit(-1);
}
return ERROR_OK;
return retval;
}
int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
cortex_m3_write_memory(target, address, 4, count, buffer);
return ERROR_OK;
return cortex_m3_write_memory(target, address, 4, count, buffer);
}
void cortex_m3_build_reg_cache(target_t *target)
......
......@@ -134,8 +134,7 @@ typedef struct cortex_m3_dwt_comparator_s
typedef struct cortex_m3_common_s
{
int common_magic;
/* int (*full_context)(struct target_s *target); */
arm_jtag_t jtag_info;
/* Context information */
......@@ -159,32 +158,8 @@ typedef struct cortex_m3_common_s
int intlinesnum;
u32 *intsetenable;
/*
u32 arm_bkpt;
u16 thumb_bkpt;
int sw_bkpts_use_wp;
int wp_available;
int wp0_used;
int wp1_used;
int force_hw_bkpts;
int dbgreq_adjust_pc;
int use_dbgrq;
int has_etm;
int reinit_embeddedice;
struct working_area_s *dcc_working_area;
int fast_memory_access;
int dcc_downloads;
*/
/* breakpoint use map */
int sw_bkpts_enabled;
armv7m_common_t armv7m;
swjdp_common_t swjdp_info;
void *arch_info;
} cortex_m3_common_t;
......
This diff is collapsed.
......@@ -34,25 +34,25 @@
#define DP_SELECT 0x8
#define DP_RDBUFF 0xC
#define CORUNDETECT (1<<0)
#define SSTICKYORUN (1<<1)
#define SSTICKYERR (1<<5)
#define CDBGRSTREQ (1<<26)
#define CDBGRSTACK (1<<27)
#define CORUNDETECT (1<<0)
#define SSTICKYORUN (1<<1)
#define SSTICKYERR (1<<5)
#define CDBGRSTREQ (1<<26)
#define CDBGRSTACK (1<<27)
#define CDBGPWRUPREQ (1<<28)
#define CDBGPWRUPACK (1<<29)
#define CSYSPWRUPREQ (1<<30)
#define CSYSPWRUPACK (1<<31)
#define AHBAP_CSW 0x00
#define AHBAP_TAR 0x04
#define AHBAP_DRW 0x0C
#define AHBAP_BD0 0x10
#define AHBAP_BD1 0x14
#define AHBAP_BD2 0x18
#define AHBAP_BD3 0x1C
#define AHBAP_CSW 0x00
#define AHBAP_TAR 0x04
#define AHBAP_DRW 0x0C
#define AHBAP_BD0 0x10
#define AHBAP_BD1 0x14
#define AHBAP_BD2 0x18
#define AHBAP_BD3 0x1C
#define AHBAP_DBGROMA 0xF8
#define AHBAP_IDR 0xFC
#define AHBAP_IDR 0xFC
#define CSW_8BIT 0
#define CSW_16BIT 1
......@@ -67,9 +67,9 @@
#define CSW_DBGSWENABLE (1<<31)
/* transaction mode */
#define TRANS_MODE_NONE 0
#define TRANS_MODE_NONE 0
/* Transaction waits for previous to complete */
#define TRANS_MODE_ATOMIC 1
#define TRANS_MODE_ATOMIC 1
/* Freerunning transactions with delays and overrun checking */
#define TRANS_MODE_COMPOSITE 2
......@@ -88,12 +88,10 @@ typedef struct swjdp_common_s
u32 dp_select_value;
u32 ap_csw_value;
u32 ap_tar_value;
u8 prev_ack;
/* information about current pending SWjDP-AHBAP transaction */
u8 trans_mode;
u8 trans_rw;
u8 ack;
u32 *trans_value;
} swjdp_common_t;
/* Internal functions used in the module, partial transactions, use with caution */
......@@ -113,17 +111,18 @@ extern int swjdp_transaction_endcheck(swjdp_common_t *swjdp);
/* Host endian word transfer of single memory and system registers */
extern int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
extern int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value);
/* Target endian (u8*) buffer transfers of blocks of memory and system registers */
extern int ahbap_read_block(swjdp_common_t *swjdp, u8 *buffer, int bytecount, u32 address);
extern int ahbap_write_block(swjdp_common_t *swjdp, u8 *buffer, int bytecount, u32 address);
/* Host endian word transfers of processor core registers */
extern int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum);
extern int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum);
extern int ahbap_read_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
extern int ahbap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
extern int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
extern int ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
extern int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
extern int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
extern int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
extern int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
/* Initialisation of the debug system, power domains and registers */
extern int ahbap_debugport_init(swjdp_common_t *swjdp);
......
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