Commit 0f1163e8 authored by Zachary T Welch's avatar Zachary T Welch
Browse files

target_t -> struct target

Remove misleading typedef and redundant suffix from struct target.
parent d0dee7cc
......@@ -30,8 +30,8 @@
static int aduc702x_build_sector_list(struct flash_bank_s *bank);
static int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms);
static int aduc702x_set_write_enable(target_t *target, int enable);
static int aduc702x_check_flash_completion(struct target* target, unsigned int timeout_ms);
static int aduc702x_set_write_enable(struct target *target, int enable);
#define ADUC702x_FLASH 0xfffff800
#define ADUC702x_FLASH_FEESTA (0*4)
......@@ -98,7 +98,7 @@ static int aduc702x_erase(struct flash_bank_s *bank, int first, int last)
int x;
int count;
//uint32_t v;
target_t *target = bank->target;
struct target *target = bank->target;
aduc702x_set_write_enable(target, 1);
......@@ -159,7 +159,7 @@ static int aduc702x_protect(struct flash_bank_s *bank, int set, int first, int l
static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct aduc702x_flash_bank *aduc702x_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
uint32_t buffer_size = 7000;
struct working_area *source;
uint32_t address = bank->base + offset;
......@@ -305,7 +305,7 @@ static int aduc702x_write_single(struct flash_bank_s *bank, uint8_t *buffer, uin
{
uint32_t x;
uint8_t b;
target_t *target = bank->target;
struct target *target = bank->target;
aduc702x_set_write_enable(target, 1);
......@@ -379,7 +379,7 @@ static int aduc702x_info(struct flash_bank_s *bank, char *buf, int buf_size)
/* sets FEEMOD bit 3
* enable = 1 enables writes & erases, 0 disables them */
static int aduc702x_set_write_enable(target_t *target, int enable)
static int aduc702x_set_write_enable(struct target *target, int enable)
{
// don't bother to preserve int enable bit here
target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
......@@ -392,7 +392,7 @@ static int aduc702x_set_write_enable(target_t *target, int enable)
*
* this function sleeps 1ms between checks (after the first one),
* so in some cases may slow things down without a usleep after the first read */
static int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms)
static int aduc702x_check_flash_completion(struct target* target, unsigned int timeout_ms)
{
uint8_t v = 4;
......
......@@ -41,7 +41,7 @@
*/
int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
{
target_t *target = nand->target;
struct target *target = nand->target;
struct armv4_5_algorithm algo;
struct arm *armv4_5 = target->arch_info;
struct reg_param reg_params[3];
......
......@@ -6,7 +6,7 @@
struct arm_nand_data {
/* target is proxy for some ARM core */
struct target_s *target;
struct target *target;
/* copy_area holds write-to-NAND loop and data to write */
struct working_area *copy_area;
......
......@@ -215,7 +215,7 @@ struct sam3_chip {
// this is "initialized" from the global const structure
struct sam3_chip_details details;
target_t *target;
struct target *target;
struct sam3_cfg cfg;
struct membuf *mbuf;
......@@ -233,7 +233,7 @@ static struct sam3_chip *all_sam3_chips;
static struct sam3_chip *
get_current_sam3(struct command_context_s *cmd_ctx)
{
target_t *t;
struct target *t;
static struct sam3_chip *p;
t = get_current_target(cmd_ctx);
......@@ -1393,7 +1393,7 @@ sam3_explain_mckr(struct sam3_chip *pChip)
#if 0
static struct sam3_chip *
target2sam3(target_t *pTarget)
target2sam3(struct target *pTarget)
{
struct sam3_chip *pChip;
......
......@@ -55,9 +55,9 @@
static int at91sam7_protect_check(struct flash_bank_s *bank);
static int at91sam7_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
static uint32_t at91sam7_get_flash_status(target_t *target, int bank_number);
static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
static uint32_t at91sam7_wait_status_busy(flash_bank_t *bank, uint32_t waitbits, int timeout);
static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number);
static void at91sam7_set_flash_mode(struct flash_bank_s *bank, int mode);
static uint32_t at91sam7_wait_status_busy(struct flash_bank_s *bank, uint32_t waitbits, int timeout);
static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen);
static uint32_t MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
......@@ -88,7 +88,7 @@ static long SRAMSIZ[16] = {
#endif
static uint32_t at91sam7_get_flash_status(target_t *target, int bank_number)
static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number)
{
uint32_t fsr;
target_read_u32(target, MC_FSR[bank_number], &fsr);
......@@ -100,7 +100,7 @@ static uint32_t at91sam7_get_flash_status(target_t *target, int bank_number)
static void at91sam7_read_clock_info(flash_bank_t *bank)
{
struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
uint32_t mckr, mcfr, pllr, mor;
unsigned long tmp = 0, mainfreq;
......@@ -180,7 +180,7 @@ static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode)
{
uint32_t fmr, fmcn = 0, fws = 0;
struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
if (mode && (mode != at91sam7_info->flashmode))
{
......@@ -255,7 +255,7 @@ static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16
{
uint32_t fcr;
struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
target_write_u32(target, MC_FCR[bank->bank_number], fcr);
......@@ -284,7 +284,7 @@ static int at91sam7_read_part_info(struct flash_bank_s *bank)
{
flash_bank_t *t_bank = bank;
struct at91sam7_flash_bank *at91sam7_info;
target_t *target = t_bank->target;
struct target *target = t_bank->target;
uint16_t bnk, sec;
uint16_t arch;
......@@ -597,7 +597,7 @@ static int at91sam7_read_part_info(struct flash_bank_s *bank)
static int at91sam7_erase_check(struct flash_bank_s *bank)
{
target_t *target = bank->target;
struct target *target = bank->target;
uint16_t retval;
uint32_t blank;
uint16_t fast_check;
......@@ -715,7 +715,7 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
{
flash_bank_t *t_bank = bank;
struct at91sam7_flash_bank *at91sam7_info;
target_t *target = t_bank->target;
struct target *target = t_bank->target;
uint32_t base_address;
uint32_t bank_size;
......@@ -949,7 +949,7 @@ static int at91sam7_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t o
{
int retval;
struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
uint32_t dst_min_alignment, wcount, bytes_remaining = count;
uint32_t first_page, last_page, pagen, buffer_pos;
......
......@@ -212,7 +212,7 @@ static int avrf_protect(struct flash_bank_s *bank, int set, int first, int last)
static int avrf_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
target_t *target = bank->target;
struct target *target = bank->target;
struct avr_common *avr = target->arch_info;
uint32_t cur_size, cur_buffer_size, page_size;
......@@ -263,7 +263,7 @@ static int avrf_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offse
#define EXTRACT_VER(X) (((X) & 0xf0000000) >> 28)
static int avrf_probe(struct flash_bank_s *bank)
{
target_t *target = bank->target;
struct target *target = bank->target;
struct avrf_flash_bank *avrf_info = bank->driver_priv;
struct avr_common *avr = target->arch_info;
struct avrf_type *avr_info = NULL;
......@@ -345,7 +345,7 @@ static int avrf_protect_check(struct flash_bank_s *bank)
static int avrf_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
target_t *target = bank->target;
struct target *target = bank->target;
struct avr_common *avr = target->arch_info;
struct avrf_type *avr_info = NULL;
int i;
......@@ -396,7 +396,7 @@ static int avrf_info(struct flash_bank_s *bank, char *buf, int buf_size)
static int avrf_mass_erase(struct flash_bank_s *bank)
{
target_t *target = bank->target;
struct target *target = bank->target;
struct avr_common *avr = target->arch_info;
if (target->state != TARGET_HALTED)
......
......@@ -136,7 +136,7 @@ static void cfi_command(flash_bank_t *bank, uint8_t cmd, uint8_t *cmd_buf)
*/
static uint8_t cfi_query_u8(flash_bank_t *bank, int sector, uint32_t offset)
{
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t data[CFI_MAX_BUS_WIDTH];
target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
......@@ -153,7 +153,7 @@ static uint8_t cfi_query_u8(flash_bank_t *bank, int sector, uint32_t offset)
*/
static uint8_t cfi_get_u8(flash_bank_t *bank, int sector, uint32_t offset)
{
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t data[CFI_MAX_BUS_WIDTH];
int i;
......@@ -178,7 +178,7 @@ static uint8_t cfi_get_u8(flash_bank_t *bank, int sector, uint32_t offset)
static uint16_t cfi_query_u16(flash_bank_t *bank, int sector, uint32_t offset)
{
target_t *target = bank->target;
struct target *target = bank->target;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
uint8_t data[CFI_MAX_BUS_WIDTH * 2];
......@@ -200,7 +200,7 @@ static uint16_t cfi_query_u16(flash_bank_t *bank, int sector, uint32_t offset)
static uint32_t cfi_query_u32(flash_bank_t *bank, int sector, uint32_t offset)
{
target_t *target = bank->target;
struct target *target = bank->target;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
uint8_t data[CFI_MAX_BUS_WIDTH * 4];
......@@ -223,7 +223,7 @@ static uint32_t cfi_query_u32(flash_bank_t *bank, int sector, uint32_t offset)
static void cfi_intel_clear_status_register(flash_bank_t *bank)
{
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
if (target->state != TARGET_HALTED)
......@@ -317,7 +317,7 @@ static int cfi_read_intel_pri_ext(flash_bank_t *bank)
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_intel_pri_ext *pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
cfi_info->pri_ext = pri_ext;
......@@ -383,7 +383,7 @@ static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
cfi_info->pri_ext = pri_ext;
......@@ -449,7 +449,7 @@ static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
struct cfi_atmel_pri_ext atmel_pri_ext;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
/* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
......@@ -656,7 +656,7 @@ static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
int i;
......@@ -701,7 +701,7 @@ static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
int i;
......@@ -802,7 +802,7 @@ static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
int retry = 0;
int i;
......@@ -949,7 +949,7 @@ static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
/* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
static void cfi_add_byte(struct flash_bank_s *bank, uint8_t *word, uint8_t byte)
{
/* target_t *target = bank->target; */
/* struct target *target = bank->target; */
int i;
......@@ -982,7 +982,7 @@ static void cfi_add_byte(struct flash_bank_s *bank, uint8_t *word, uint8_t byte)
/* Convert code image to target endian */
/* FIXME create general block conversion fcts in target.c?) */
static void cfi_fix_code_endian(target_t *target, uint8_t *dest, const uint32_t *src, uint32_t count)
static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
{
uint32_t i;
for (i = 0; i< count; i++)
......@@ -995,7 +995,7 @@ static void cfi_fix_code_endian(target_t *target, uint8_t *dest, const uint32_t
static uint32_t cfi_command_val(flash_bank_t *bank, uint8_t cmd)
{
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t buf[CFI_MAX_BUS_WIDTH];
cfi_command(bank, cmd, buf);
......@@ -1019,7 +1019,7 @@ static uint32_t cfi_command_val(flash_bank_t *bank, uint8_t cmd)
static int cfi_intel_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t address, uint32_t count)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
struct reg_param reg_params[7];
struct armv4_5_algorithm armv4_5_info;
struct working_area *source;
......@@ -1264,7 +1264,7 @@ static int cfi_spansion_write_block(struct flash_bank_s *bank, uint8_t *buffer,
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
struct target *target = bank->target;
struct reg_param reg_params[10];
struct armv4_5_algorithm armv4_5_info;
struct working_area *source;
......@@ -1563,7 +1563,7 @@ static int cfi_intel_write_word(struct flash_bank_s *bank, uint8_t *word, uint32
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
cfi_intel_clear_status_register(bank);
......@@ -1597,7 +1597,7 @@ static int cfi_intel_write_words(struct flash_bank_s *bank, uint8_t *word, uint3
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
/* Calculate buffer size and boundary mask */
......@@ -1691,7 +1691,7 @@ static int cfi_spansion_write_word(struct flash_bank_s *bank, uint8_t *word, uin
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
cfi_command(bank, 0xaa, command);
......@@ -1736,7 +1736,7 @@ static int cfi_spansion_write_words(struct flash_bank_s *bank, uint8_t *word, ui
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
......@@ -1869,7 +1869,7 @@ static int cfi_write_words(struct flash_bank_s *bank, uint8_t *word, uint32_t wo
int cfi_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
uint32_t address = bank->base + offset; /* address of first byte to be programmed */
uint32_t write_p, copy_p;
int align; /* number of unaligned bytes */
......@@ -2121,7 +2121,7 @@ static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
static int cfi_query_string(struct flash_bank_s *bank, int address)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
int retval;
uint8_t command[8];
......@@ -2159,7 +2159,7 @@ static int cfi_query_string(struct flash_bank_s *bank, int address)
static int cfi_probe(struct flash_bank_s *bank)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
int num_sectors = 0;
int i;
......@@ -2449,7 +2449,7 @@ static int cfi_intel_protect_check(struct flash_bank_s *bank)
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[CFI_MAX_BUS_WIDTH];
int i;
......@@ -2482,7 +2482,7 @@ static int cfi_spansion_protect_check(struct flash_bank_s *bank)
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
struct target *target = bank->target;
uint8_t command[8];
int i;
......
......@@ -38,7 +38,7 @@ enum ecc {
};
struct davinci_nand {
target_t *target;
struct target *target;
uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */
uint8_t eccmode;
......@@ -69,7 +69,7 @@ struct davinci_nand {
#define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */
#define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */
static int halted(target_t *target, const char *label)
static int halted(struct target *target, const char *label)
{
if (target->state == TARGET_HALTED)
return true;
......@@ -86,7 +86,7 @@ static int davinci_register_commands(struct command_context_s *cmd_ctx)
static int davinci_init(struct nand_device_s *nand)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
struct target *target = info->target;
uint32_t nandfcr;
if (!halted(target, "init"))
......@@ -116,7 +116,7 @@ static int davinci_reset(struct nand_device_s *nand)
static int davinci_nand_ready(struct nand_device_s *nand, int timeout)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
struct target *target = info->target;
uint32_t nandfsr;
/* NOTE: return code is zero/error, else success; not ERROR_* */
......@@ -139,7 +139,7 @@ static int davinci_nand_ready(struct nand_device_s *nand, int timeout)
static int davinci_command(struct nand_device_s *nand, uint8_t command)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
struct target *target = info->target;
if (!halted(target, "command"))
return ERROR_NAND_OPERATION_FAILED;
......@@ -151,7 +151,7 @@ static int davinci_command(struct nand_device_s *nand, uint8_t command)
static int davinci_address(struct nand_device_s *nand, uint8_t address)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
struct target *target = info->target;
if (!halted(target, "address"))
return ERROR_NAND_OPERATION_FAILED;
......@@ -163,7 +163,7 @@ static int davinci_address(struct nand_device_s *nand, uint8_t address)
static int davinci_write_data(struct nand_device_s *nand, uint16_t data)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
struct target *target = info->target;
if (!halted(target, "write_data"))
return ERROR_NAND_OPERATION_FAILED;
......@@ -175,7 +175,7 @@ static int davinci_write_data(struct nand_device_s *nand, uint16_t data)
static int davinci_read_data(struct nand_device_s *nand, void *data)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
struct target *target = info->target;
if (!halted(target, "read_data"))
return ERROR_NAND_OPERATION_FAILED;
......@@ -190,7 +190,7 @@ static int davinci_read_block_data(struct nand_device_s *nand,
uint8_t *data, int data_size)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
struct target *target = info->target;
uint32_t nfdata = info->data;
uint32_t tmp;
......@@ -223,7 +223,7 @@ static int davinci_write_block_data(struct nand_device_s *nand,
uint8_t *data, int data_size)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
struct target *target = info->target;
uint32_t nfdata = info->data;
uint32_t tmp;
int status;
......@@ -322,7 +322,7 @@ static int davinci_read_page(struct nand_device_s *nand, uint32_t page,
static void davinci_write_pagecmd(struct nand_device_s *nand, uint8_t cmd, uint32_t page)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
struct target *target = info->target;
int page3 = nand->address_cycles - (nand->page_size == 512);
/* write command ({page,otp}x{read,program} */
......@@ -346,7 +346,7 @@ static int davinci_writepage_tail(struct nand_device_s *nand,
uint8_t *oob, uint32_t oob_size)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
struct target *target = info->target;
uint8_t status;
if (oob_size)
......@@ -379,7 +379,7 @@ static int davinci_write_page_ecc1(struct nand_device_s *nand, uint32_t page,
{
unsigned oob_offset;
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
struct target *target = info->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel);
uint32_t fcr, ecc1;
......@@ -467,7 +467,7 @@ static int davinci_write_page_ecc4(struct nand_device_s *nand, uint32_t page,
struct davinci_nand *info = nand->controller_priv;
const uint8_t *l;
target_t *target = info->target;
struct target *target = info->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
uint32_t fcr, ecc4;
......@@ -547,7 +547,7 @@ static int davinci_write_page_ecc4infix(struct nand_device_s *nand, uint32_t pag
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
struct target *target = info->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
uint32_t fcr, ecc4;
......@@ -632,7 +632,7 @@ static int davinci_read_page_ecc4infix(struct nand_device_s *nand, uint32_t page
NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command)
{
struct davinci_nand *info;
target_t *target;
struct target *target;
unsigned long chip, aemif;
enum ecc eccmode;
int chipsel;
......
......@@ -35,7 +35,7 @@ static int ecosflash_handle_gpnvm_command(struct command_context_s *cmd_ctx, cha
struct ecosflash_flash_bank
{
struct target_s *target;
struct target *target;
struct working_area *write_algorithm;
struct working_area *erase_check_algorithm;
char *driverPath;
......@@ -157,7 +157,7 @@ static int loadDriver(struct ecosflash_flash_bank *info)
image.base_address_set = 0;
image.start_address_set = 0;
target_t *target = info->target;
struct target *target = info->target;
int retval;
if ((retval = image_open(&image, info->driverPath, NULL)) != ERROR_OK)
......@@ -204,7 +204,7 @@ static int runCode(struct ecosflash_flash_bank *info,
/* timeout in ms */
int timeout)
{
target_t *target = info->target;
struct target *target = info->target;
struct reg_param reg_params[3];
struct armv4_5_algorithm armv4_5_info;
......@@ -272,7 +272,7 @@ static int eCosBoard_erase(struct ecosflash_flash_bank *info, uint32_t address,
static int eCosBoard_flash(struct ecosflash_flash_bank *info, void *data, uint32_t address, uint32_t len)
{
target_t *target = info->target;
struct target *target = info->target;
const int chunk = 8192;
int retval = ERROR_OK;
int timeout = (chunk / 20480 + 1) * 1000; /*asume 20 KB/s + 1 second*/
......
......@@ -27,7 +27,7 @@
struct faux_flash_bank
{
struct target_s *target;
struct target *target;
uint8_t *memory;
uint32_t start_address;
};
......
......@@ -31,7 +31,7 @@
#include "image.h"
#include "time_support.h"
static int flash_write_unlock(target_t *target, struct image *image, uint32_t *written, int erase, bool unlock