Commit 0cba0d4d authored by ntfreak's avatar ntfreak
Browse files

- remove target specific variant and use target->variant member

- fix build warning in cortex_m3
- code cleanup - remove trailing lf and convert c++ comments

git-svn-id: svn://svn.berlios.de/openocd/trunk@1238 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 846a2589
......@@ -188,8 +188,6 @@ int telnet_new_connection(connection_t *connection)
log_add_callback(telnet_log_callback, connection);
return ERROR_OK;
}
......
......@@ -447,21 +447,19 @@ int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *targ
arm7tdmi_init_target(cmd_ctx, target);
return ERROR_OK;
}
int arm720t_quit(void)
{
return ERROR_OK;
}
int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap, const char *variant)
int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap)
{
arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
arm7tdmi_init_arch_info(target, arm7tdmi, tap, variant);
arm7tdmi_init_arch_info(target, arm7tdmi, tap);
arm7tdmi->arch_info = arm720t;
arm720t->common_magic = ARM720T_COMMON_MAGIC;
......@@ -485,7 +483,7 @@ int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
{
arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
arm720t_init_arch_info(target, arm720t, target->tap, target->variant);
arm720t_init_arch_info(target, arm720t, target->tap);
return ERROR_OK;
}
......
......@@ -66,7 +66,6 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx,
int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
{
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
......@@ -143,7 +142,6 @@ int arm7_9_setup(target_t *target)
return arm7_9_clear_watchpoints(arm7_9);
}
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
{
armv4_5_common_t *armv4_5 = target->arch_info;
......@@ -269,7 +267,6 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
}
return retval;
}
int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
......@@ -388,7 +385,6 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
}
}
arm7_9->breakpoint_count++;
return arm7_9_set_breakpoint(target, breakpoint);
......@@ -571,9 +567,6 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
return ERROR_OK;
}
int arm7_9_execute_sys_speed(struct target_s *target)
{
int retval;
......@@ -642,9 +635,9 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
/* check for DBGACK and SYSCOMP set (others don't care) */
/* NB! These are constants that must be available until after next jtag_execute() and
we evaluate the values upon first execution in lieu of setting up these constants
during early setup.
*/
* we evaluate the values upon first execution in lieu of setting up these constants
* during early setup.
* */
buf_set_u32(check_value, 0, 32, 0x9);
buf_set_u32(check_mask, 0, 32, 0x9);
set=1;
......@@ -689,7 +682,6 @@ int arm7_9_handle_target_request(void *priv)
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
if (!target->dbg_msg_enabled)
return ERROR_OK;
......@@ -857,7 +849,6 @@ int arm7_9_assert_reset(target_t *target)
jtag_add_reset(0, 1);
}
target->state = TARGET_RESET;
jtag_add_sleep(50000);
......@@ -870,7 +861,6 @@ int arm7_9_assert_reset(target_t *target)
}
return ERROR_OK;
}
int arm7_9_deassert_reset(target_t *target)
......@@ -879,7 +869,6 @@ int arm7_9_deassert_reset(target_t *target)
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
/* deassert reset lines */
jtag_add_reset(0, 0);
......@@ -1527,7 +1516,6 @@ void arm7_9_enable_breakpoints(struct target_s *target)
}
}
int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
{
armv4_5_common_t *armv4_5 = target->arch_info;
......@@ -1833,7 +1821,6 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
}
return err;
}
int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
......@@ -1900,7 +1887,6 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
}
return ERROR_OK;
}
int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
......@@ -2326,7 +2312,6 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
static int dcc_count;
static u8 *dcc_buffer;
static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
{
int retval = ERROR_OK;
......@@ -2342,8 +2327,7 @@ static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int ti
if (count>2)
{
/* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
core function repeated.
*/
* core function repeated. */
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
buffer+=4;
......@@ -2373,7 +2357,6 @@ static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int ti
return target_wait_state(target, TARGET_HALTED, 500);
}
static const u32 dcc_code[] =
{
/* MRC TST BNE MRC STR B */
......@@ -2382,7 +2365,6 @@ static const u32 dcc_code[] =
int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info));
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
int retval;
......@@ -2429,8 +2411,6 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
buf_set_u32(reg_params[0].value, 0, 32, address);
//armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
// int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
dcc_count=count;
dcc_buffer=buffer;
retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
......@@ -2741,10 +2721,8 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char
value = strtoul(args[2], NULL, 0);
return arm7_9_write_core_reg(target, num, mode, value);
}
int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
......
......@@ -154,5 +154,4 @@ int arm7_9_execute_sys_speed(struct target_s *target);
int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p);
#endif /* ARM7_9_COMMON_H */
......@@ -364,7 +364,6 @@ void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
* reading PC in Thumb state gives address of instruction + 4
*/
*pc -= 0xa;
}
void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
......@@ -391,7 +390,6 @@ void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
/* nothing fetched, STM still in EXECUTE (1+i cycle) */
arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
}
}
void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
......@@ -435,7 +433,6 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
}
}
}
}
void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
......@@ -456,7 +453,6 @@ void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* nothing fetched, STR still in EXECUTE (2nd cycle) */
arm7tdmi_clock_data_in(jtag_info, xpsr);
}
void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
......@@ -507,7 +503,6 @@ void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* nothing fetched, MSR in EXECUTE (2) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
}
void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
......@@ -535,7 +530,6 @@ void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
}
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
}
void arm7tdmi_load_word_regs(target_t *target, u32 mask)
......@@ -549,7 +543,6 @@ void arm7tdmi_load_word_regs(target_t *target, u32 mask)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
}
void arm7tdmi_load_hword_reg(target_t *target, int num)
......@@ -563,7 +556,6 @@ void arm7tdmi_load_hword_reg(target_t *target, int num)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
}
void arm7tdmi_load_byte_reg(target_t *target, int num)
......@@ -577,7 +569,6 @@ void arm7tdmi_load_byte_reg(target_t *target, int num)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
}
void arm7tdmi_store_word_regs(target_t *target, u32 mask)
......@@ -591,7 +582,6 @@ void arm7tdmi_store_word_regs(target_t *target, u32 mask)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
}
void arm7tdmi_store_hword_reg(target_t *target, int num)
......@@ -605,7 +595,6 @@ void arm7tdmi_store_hword_reg(target_t *target, int num)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
}
void arm7tdmi_store_byte_reg(target_t *target, int num)
......@@ -619,7 +608,6 @@ void arm7tdmi_store_byte_reg(target_t *target, int num)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
}
void arm7tdmi_write_pc(target_t *target, u32 pc)
......@@ -658,7 +646,6 @@ void arm7tdmi_branch_resume(target_t *target)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
}
void arm7tdmi_branch_resume_thumb(target_t *target)
......@@ -720,7 +707,6 @@ void arm7tdmi_branch_resume_thumb(target_t *target)
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
}
void arm7tdmi_build_reg_cache(target_t *target)
......@@ -771,20 +757,17 @@ int arm7tdmi_examine(struct target_s *target)
int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
arm7tdmi_build_reg_cache(target);
return ERROR_OK;
}
int arm7tdmi_quit(void)
{
return ERROR_OK;
}
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap, const char *variant)
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap)
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
......@@ -838,34 +821,21 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_
arm7tdmi->arch_info = NULL;
arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
if (variant)
{
arm7tdmi->variant = strdup(variant);
}
else
{
arm7tdmi->variant = strdup("");
}
arm7_9_init_arch_info(target, arm7_9);
return ERROR_OK;
}
int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
{
arm7tdmi_common_t *arm7tdmi;
arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
arm7tdmi_init_arch_info(target, arm7tdmi, target->tap, target->variant);
arm7tdmi_init_arch_info(target, arm7tdmi, target->tap);
return ERROR_OK;
}
int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
{
int retval;
......@@ -873,5 +843,4 @@ int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
retval = arm7_9_register_commands(cmd_ctx);
return retval;
}
......@@ -35,15 +35,13 @@
typedef struct arm7tdmi_common_s
{
int common_magic;
char *variant;
void *arch_info;
arm7_9_common_t arm7_9_common;
} arm7tdmi_common_t;
int arm7tdmi_register_commands(struct command_context_s *cmd_ctx);
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap, const char *variant);
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap);
int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm7tdmi_examine(struct target_s *target);
#endif /* ARM7TDMI_H */
......@@ -703,23 +703,21 @@ int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *targ
arm9tdmi_init_target(cmd_ctx, target);
return ERROR_OK;
}
int arm920t_quit(void)
{
return ERROR_OK;
}
int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap, const char *variant)
int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
arm9tdmi_init_arch_info(target, arm9tdmi, tap);
arm9tdmi->arch_info = arm920t;
arm920t->common_magic = ARM920T_COMMON_MAGIC;
......@@ -752,7 +750,7 @@ int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
{
arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
arm920t_init_arch_info(target, arm920t, target->tap, target->variant);
arm920t_init_arch_info(target, arm920t, target->tap);
return ERROR_OK;
}
......@@ -995,10 +993,8 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
i_cache[segment][index].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
}
}
/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
......
......@@ -98,7 +98,6 @@ target_type_t arm926ejs_target =
.mmu = arm926ejs_mmu
};
int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
{
/* The ARM926EJ-S' instruction register is 4 bits wide */
......@@ -498,7 +497,6 @@ void arm926ejs_post_debug_entry(target_t *target)
LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
u32 cache_dbg_ctrl;
/* read-modify-write CP15 cache debug control register
......@@ -666,7 +664,6 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
......@@ -705,23 +702,21 @@ int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
arm9tdmi_init_target(cmd_ctx, target);
return ERROR_OK;
}
int arm926ejs_quit(void)
{
return ERROR_OK;
}
int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap, const char *variant)
int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
arm9tdmi_init_arch_info(target, arm9tdmi, tap);
arm9tdmi->arch_info = arm926ejs;
arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
......@@ -755,7 +750,7 @@ int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
{
arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
arm926ejs_init_arch_info(target, arm926ejs, target->tap);
return ERROR_OK;
}
......@@ -945,6 +940,7 @@ int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char
return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
}
static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
{
int retval;
......
......@@ -43,7 +43,7 @@ typedef struct arm926ejs_common_s
u32 d_far;
} arm926ejs_common_t;
extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap, const char *variant);
extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap);
extern int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
extern int arm926ejs_arch_state(struct target_s *target);
extern int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
......
......@@ -98,16 +98,15 @@ int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *targ
int arm966e_quit(void)
{
return ERROR_OK;
}
int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap_t *tap, const char *variant)
int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap_t *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
arm9tdmi_init_arch_info(target, arm9tdmi, tap);
arm9tdmi->arch_info = arm966e;
arm966e->common_magic = ARM966E_COMMON_MAGIC;
......@@ -125,7 +124,7 @@ int arm966e_target_create( struct target_s *target, Jim_Interp *interp )
{
arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t));
arm966e_init_arch_info(target, arm966e, target->tap, target->variant);
arm966e_init_arch_info(target, arm966e, target->tap);
return ERROR_OK;
}
......
......@@ -507,7 +507,6 @@ void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
/* nothing fetched, STM in MEMORY (i'th cycle) */
arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
}
}
void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
......@@ -549,7 +548,6 @@ void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
break;
}
}
}
void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
......@@ -574,7 +572,6 @@ void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
/* nothing fetched, STR in MEMORY */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
}
void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
......@@ -664,7 +661,6 @@ void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
}
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
void arm9tdmi_load_word_regs(target_t *target, u32 mask)
......@@ -677,7 +673,6 @@ void arm9tdmi_load_word_regs(target_t *target, u32 mask)
/* put system-speed load-multiple into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
void arm9tdmi_load_hword_reg(target_t *target, int num)
......@@ -702,7 +697,6 @@ void arm9tdmi_load_byte_reg(target_t *target, int num)
/* put system-speed load byte into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
void arm9tdmi_store_word_regs(target_t *target, u32 mask)
......@@ -715,7 +709,6 @@ void arm9tdmi_store_word_regs(target_t *target, u32 mask)
/* put system-speed store-multiple into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
void arm9tdmi_store_hword_reg(target_t *target, int num)
......@@ -728,7 +721,6 @@ void arm9tdmi_store_hword_reg(target_t *target, int num)
/* put system-speed store half-word into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
void arm9tdmi_store_byte_reg(target_t *target, int num)
......@@ -741,7 +733,6 @@ void arm9tdmi_store_byte_reg(target_t *target, int num)
/* put system-speed store byte into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
void arm9tdmi_write_pc(target_t *target, u32 pc)
......@@ -768,7 +759,6 @@ void arm9tdmi_write_pc(target_t *target, u32 pc)
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
/* fetch NOP, LDM in EXECUTE stage (5th cycle) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
void arm9tdmi_branch_resume(target_t *target)
......@@ -780,7 +770,6 @@ void arm9tdmi_branch_resume(target_t *target)
arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
void arm9tdmi_branch_resume_thumb(target_t *target)
......@@ -841,7 +830,6 @@ void arm9tdmi_branch_resume_thumb(target_t *target)
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);