Commit 069a04dc authored by oharboe's avatar oharboe
Browse files

Hongtao Zheng single step fixes

git-svn-id: svn://svn.berlios.de/openocd/trunk@1113 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent b8f895de
......@@ -1553,6 +1553,9 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
if (!current)
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
u32 current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
{
......@@ -1564,8 +1567,18 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
return retval;
}
/* calculate PC of next instruction */
u32 next_pc;
if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
{
u32 current_opcode;
target_read_u32(target, current_pc, &current_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
return retval;
}
LOG_DEBUG("enable single-step");
arm7_9->enable_single_step(target);
arm7_9->enable_single_step(target, next_pc);
target->debug_reason = DBG_REASON_SINGLESTEP;
......@@ -1675,23 +1688,13 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
return ERROR_OK;
}
void arm7_9_enable_eice_step(target_t *target)
void arm7_9_enable_eice_step(target_t *target, u32 next_pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int retval;
u32 current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
u32 next_pc;
if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
{
u32 current_opcode;
target_read_u32(target, current_pc, &current_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
return;
}
if(next_pc != current_pc)
{
......@@ -1756,6 +1759,9 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
if (!current)
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
u32 current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
......@@ -1766,12 +1772,22 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
target->debug_reason = DBG_REASON_SINGLESTEP;
/* calculate PC of next instruction */
u32 next_pc;
if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
{
u32 current_opcode;
target_read_u32(target, current_pc, &current_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
return retval;
}
if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
{
return retval;
}
arm7_9->enable_single_step(target);
arm7_9->enable_single_step(target, next_pc);
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
{
......
......@@ -8,6 +8,9 @@
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2008 by Hongtao Zheng *
* hontor@126.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
......@@ -93,7 +96,7 @@ typedef struct arm7_9_common_s
void (*branch_resume)(target_t *target);
void (*branch_resume_thumb)(target_t *target);
void (*enable_single_step)(target_t *target);
void (*enable_single_step)(target_t *target, u32 next_pc);
void (*disable_single_step)(target_t *target);
void (*set_special_dbgrq)(target_t *target);
......@@ -143,7 +146,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
void arm7_9_enable_eice_step(target_t *target);
void arm7_9_enable_eice_step(target_t *target, u32 next_pc);
void arm7_9_disable_eice_step(target_t *target);
int arm7_9_execute_sys_speed(struct target_s *target);
......
......@@ -5,6 +5,9 @@
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2008 by Hongtao Zheng *
* hontor@126.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
......@@ -841,7 +844,7 @@ void arm9tdmi_branch_resume_thumb(target_t *target)
}
void arm9tdmi_enable_single_step(target_t *target)
void arm9tdmi_enable_single_step(target_t *target, u32 next_pc)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
......@@ -854,7 +857,7 @@ void arm9tdmi_enable_single_step(target_t *target)
}
else
{
arm7_9_enable_eice_step(target);
arm7_9_enable_eice_step(target, next_pc);
}
}
......
......@@ -2,6 +2,9 @@
* Copyright (C) 2008 by Marvell Semiconductors, Inc. *
* Written by Nicolas Pitre <nico@marvell.com> *
* *
* Copyright (C) 2008 by Hongtao Zheng *
* hontor@126.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
......@@ -49,7 +52,6 @@
#include "arm926ejs.h"
#include "jtag.h"
#include "log.h"
#include "arm_simulator.h"
#include <stdlib.h>
#include <string.h>
......@@ -472,23 +474,10 @@ void feroceon_set_dbgrq(target_t *target)
embeddedice_store_reg(dbg_ctrl);
}
void feroceon_enable_single_step(target_t *target)
void feroceon_enable_single_step(target_t *target, u32 next_pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
u32 next_pc;
/* calculate PC of next instruction */
if (arm_simulate_step(target, &next_pc) != ERROR_OK)
{
u32 current_pc, current_opcode;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
target_read_u32(target, current_pc, &current_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, "
"current opcode is 0x%8.8x", current_opcode);
next_pc = current_pc;
}
arm7_9_restore_context(target);
/* set a breakpoint there */
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc);
......
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