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/***************************************************************************
 *   Copyright (C) 2013 by Andrey Yurovsky                                 *
 *   Andrey Yurovsky <yurovsky@gmail.com>                                  *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
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 *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
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 ***************************************************************************/

#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "imp.h"
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#include "helper/binarybuffer.h"
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#include <target/cortex_m.h>

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#define SAMD_NUM_PROT_BLOCKS	16
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#define SAMD_PAGE_SIZE_MAX	1024
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#define SAMD_FLASH			((uint32_t)0x00000000)	/* physical Flash memory */
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#define SAMD_USER_ROW		((uint32_t)0x00804000)	/* User Row of Flash */
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#define SAMD_PAC1			0x41000000	/* Peripheral Access Control 1 */
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#define SAMD_DSU			0x41002000	/* Device Service Unit */
#define SAMD_NVMCTRL		0x41004000	/* Non-volatile memory controller */

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#define SAMD_DSU_STATUSA        1               /* DSU status register */
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#define SAMD_DSU_DID		0x18		/* Device ID register */
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#define SAMD_DSU_CTRL_EXT	0x100		/* CTRL register, external access */
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#define SAMD_NVMCTRL_CTRLA		0x00	/* NVM control A register */
#define SAMD_NVMCTRL_CTRLB		0x04	/* NVM control B register */
#define SAMD_NVMCTRL_PARAM		0x08	/* NVM parameters register */
#define SAMD_NVMCTRL_INTFLAG	0x18	/* NVM Interupt Flag Status & Clear */
#define SAMD_NVMCTRL_STATUS		0x18	/* NVM status register */
#define SAMD_NVMCTRL_ADDR		0x1C	/* NVM address register */
#define SAMD_NVMCTRL_LOCK		0x20	/* NVM Lock section register */

#define SAMD_CMDEX_KEY		0xA5UL
#define SAMD_NVM_CMD(n)		((SAMD_CMDEX_KEY << 8) | (n & 0x7F))

/* NVMCTRL commands.  See Table 20-4 in 42129F–SAM–10/2013 */
#define SAMD_NVM_CMD_ER		0x02		/* Erase Row */
#define SAMD_NVM_CMD_WP		0x04		/* Write Page */
#define SAMD_NVM_CMD_EAR	0x05		/* Erase Auxilary Row */
#define SAMD_NVM_CMD_WAP	0x06		/* Write Auxilary Page */
#define SAMD_NVM_CMD_LR		0x40		/* Lock Region */
#define SAMD_NVM_CMD_UR		0x41		/* Unlock Region */
#define SAMD_NVM_CMD_SPRM	0x42		/* Set Power Reduction Mode */
#define SAMD_NVM_CMD_CPRM	0x43		/* Clear Power Reduction Mode */
#define SAMD_NVM_CMD_PBC	0x44		/* Page Buffer Clear */
#define SAMD_NVM_CMD_SSB	0x45		/* Set Security Bit */
#define SAMD_NVM_CMD_INVALL	0x46		/* Invalidate all caches */

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/* NVMCTRL bits */
#define SAMD_NVM_CTRLB_MANW 0x80

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/* Known identifiers */
#define SAMD_PROCESSOR_M0	0x01
#define SAMD_FAMILY_D		0x00
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#define SAMD_FAMILY_L		0x01
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#define SAMD_FAMILY_C		0x02
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#define SAMD_SERIES_20		0x00
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#define SAMD_SERIES_21		0x01
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#define SAMD_SERIES_22		0x02
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#define SAMD_SERIES_10		0x02
#define SAMD_SERIES_11		0x03
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#define SAMD_SERIES_09		0x04
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/* Device ID macros */
#define SAMD_GET_PROCESSOR(id) (id >> 28)
#define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
#define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
#define SAMD_GET_DEVSEL(id) (id & 0xFF)

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/* Bits to mask out lockbits in user row */
#define NVMUSERROW_LOCKBIT_MASK ((uint64_t)0x0000FFFFFFFFFFFF)

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struct samd_part {
	uint8_t id;
	const char *name;
	uint32_t flash_kb;
	uint32_t ram_kb;
};

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/* Known SAMD09 parts. DID reset values missing in RM, see
 * https://github.com/avrxml/asf/blob/master/sam0/utils/cmsis/samd09/include/ */
static const struct samd_part samd09_parts[] = {
	{ 0x0, "SAMD09D14A", 16, 4 },
	{ 0x7, "SAMD09C13A", 8, 4 },
};

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/* Known SAMD10 parts */
static const struct samd_part samd10_parts[] = {
	{ 0x0, "SAMD10D14AMU", 16, 4 },
	{ 0x1, "SAMD10D13AMU", 8, 4 },
	{ 0x2, "SAMD10D12AMU", 4, 4 },
	{ 0x3, "SAMD10D14ASU", 16, 4 },
	{ 0x4, "SAMD10D13ASU", 8, 4 },
	{ 0x5, "SAMD10D12ASU", 4, 4 },
	{ 0x6, "SAMD10C14A", 16, 4 },
	{ 0x7, "SAMD10C13A", 8, 4 },
	{ 0x8, "SAMD10C12A", 4, 4 },
};

/* Known SAMD11 parts */
static const struct samd_part samd11_parts[] = {
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	{ 0x0, "SAMD11D14AM", 16, 4 },
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	{ 0x1, "SAMD11D13AMU", 8, 4 },
	{ 0x2, "SAMD11D12AMU", 4, 4 },
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	{ 0x3, "SAMD11D14ASS", 16, 4 },
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	{ 0x4, "SAMD11D13ASU", 8, 4 },
	{ 0x5, "SAMD11D12ASU", 4, 4 },
	{ 0x6, "SAMD11C14A", 16, 4 },
	{ 0x7, "SAMD11C13A", 8, 4 },
	{ 0x8, "SAMD11C12A", 4, 4 },
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	{ 0x9, "SAMD11D14AU", 16, 4 },
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};

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/* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
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static const struct samd_part samd20_parts[] = {
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	{ 0x0, "SAMD20J18A", 256, 32 },
	{ 0x1, "SAMD20J17A", 128, 16 },
	{ 0x2, "SAMD20J16A", 64, 8 },
	{ 0x3, "SAMD20J15A", 32, 4 },
	{ 0x4, "SAMD20J14A", 16, 2 },
	{ 0x5, "SAMD20G18A", 256, 32 },
	{ 0x6, "SAMD20G17A", 128, 16 },
	{ 0x7, "SAMD20G16A", 64, 8 },
	{ 0x8, "SAMD20G15A", 32, 4 },
	{ 0x9, "SAMD20G14A", 16, 2 },
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	{ 0xA, "SAMD20E18A", 256, 32 },
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	{ 0xB, "SAMD20E17A", 128, 16 },
	{ 0xC, "SAMD20E16A", 64, 8 },
	{ 0xD, "SAMD20E15A", 32, 4 },
	{ 0xE, "SAMD20E14A", 16, 2 },
};

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/* Known SAMD21 parts. */
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static const struct samd_part samd21_parts[] = {
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	{ 0x0, "SAMD21J18A", 256, 32 },
	{ 0x1, "SAMD21J17A", 128, 16 },
	{ 0x2, "SAMD21J16A", 64, 8 },
	{ 0x3, "SAMD21J15A", 32, 4 },
	{ 0x4, "SAMD21J14A", 16, 2 },
	{ 0x5, "SAMD21G18A", 256, 32 },
	{ 0x6, "SAMD21G17A", 128, 16 },
	{ 0x7, "SAMD21G16A", 64, 8 },
	{ 0x8, "SAMD21G15A", 32, 4 },
	{ 0x9, "SAMD21G14A", 16, 2 },
	{ 0xA, "SAMD21E18A", 256, 32 },
	{ 0xB, "SAMD21E17A", 128, 16 },
	{ 0xC, "SAMD21E16A", 64, 8 },
	{ 0xD, "SAMD21E15A", 32, 4 },
	{ 0xE, "SAMD21E14A", 16, 2 },

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    /* SAMR21 parts have integrated SAMD21 with a radio */
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	{ 0x18, "SAMR21G19A", 256, 32 }, /* with 512k of serial flash */
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	{ 0x19, "SAMR21G18A", 256, 32 },
	{ 0x1A, "SAMR21G17A", 128, 32 },
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	{ 0x1B, "SAMR21G16A",  64, 16 },
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	{ 0x1C, "SAMR21E18A", 256, 32 },
	{ 0x1D, "SAMR21E17A", 128, 32 },
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	{ 0x1E, "SAMR21E16A",  64, 16 },
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    /* SAMD21 B Variants (Table 3-7 from rev I of datasheet) */
	{ 0x20, "SAMD21J16B", 64, 8 },
	{ 0x21, "SAMD21J15B", 32, 4 },
	{ 0x23, "SAMD21G16B", 64, 8 },
	{ 0x24, "SAMD21G15B", 32, 4 },
	{ 0x26, "SAMD21E16B", 64, 8 },
	{ 0x27, "SAMD21E15B", 32, 4 },
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	/* Known SAMDA1 parts.
	   SAMD-A1 series uses the same series identifier like the SAMD21
	   taken from http://ww1.microchip.com/downloads/en/DeviceDoc/40001895A.pdf (pages 14-17) */
	{ 0x29, "SAMDA1J16A", 64, 8 },
	{ 0x2A, "SAMDA1J15A", 32, 4 },
	{ 0x2B, "SAMDA1J14A", 16, 4 },
	{ 0x2C, "SAMDA1G16A", 64, 8 },
	{ 0x2D, "SAMDA1G15A", 32, 4 },
	{ 0x2E, "SAMDA1G14A", 16, 4 },
	{ 0x2F, "SAMDA1E16A", 64, 8 },
	{ 0x30, "SAMDA1E15A", 32, 4 },
	{ 0x31, "SAMDA1E14A", 16, 4 },
	{ 0x64, "SAMDA1J16B", 64, 8 },
	{ 0x65, "SAMDA1J15B", 32, 4 },
	{ 0x66, "SAMDA1J14B", 16, 4 },
	{ 0x67, "SAMDA1G16B", 64, 8 },
	{ 0x68, "SAMDA1G15B", 32, 4 },
	{ 0x69, "SAMDA1G14B", 16, 4 },
	{ 0x6A, "SAMDA1E16B", 64, 8 },
	{ 0x6B, "SAMDA1E15B", 32, 4 },
	{ 0x6C, "SAMDA1E14B", 16, 4 },
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};

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/* Known SAML21 parts. */
static const struct samd_part saml21_parts[] = {
	{ 0x00, "SAML21J18A", 256, 32 },
	{ 0x01, "SAML21J17A", 128, 16 },
	{ 0x02, "SAML21J16A", 64, 8 },
	{ 0x05, "SAML21G18A", 256, 32 },
	{ 0x06, "SAML21G17A", 128, 16 },
	{ 0x07, "SAML21G16A", 64, 8 },
	{ 0x0A, "SAML21E18A", 256, 32 },
	{ 0x0B, "SAML21E17A", 128, 16 },
	{ 0x0C, "SAML21E16A", 64, 8 },
	{ 0x0D, "SAML21E15A", 32, 4 },
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	{ 0x0F, "SAML21J18B", 256, 32 },
	{ 0x10, "SAML21J17B", 128, 16 },
	{ 0x11, "SAML21J16B", 64, 8 },
	{ 0x14, "SAML21G18B", 256, 32 },
	{ 0x15, "SAML21G17B", 128, 16 },
	{ 0x16, "SAML21G16B", 64, 8 },
	{ 0x19, "SAML21E18B", 256, 32 },
	{ 0x1A, "SAML21E17B", 128, 16 },
	{ 0x1B, "SAML21E16B", 64, 8 },
	{ 0x1C, "SAML21E15B", 32, 4 },
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    /* SAMR30 parts have integrated SAML21 with a radio */
	{ 0x1E, "SAMR30G18A", 256, 32 },
	{ 0x1F, "SAMR30E18A", 256, 32 },
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    /* SAMR34/R35 parts have integrated SAML21 with a lora radio */
	{ 0x28, "SAMR34J18", 256, 32 },
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};
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/* Known SAML22 parts. */
static const struct samd_part saml22_parts[] = {
	{ 0x00, "SAML22N18A", 256, 32 },
	{ 0x01, "SAML22N17A", 128, 16 },
	{ 0x02, "SAML22N16A", 64, 8 },
	{ 0x05, "SAML22J18A", 256, 32 },
	{ 0x06, "SAML22J17A", 128, 16 },
	{ 0x07, "SAML22J16A", 64, 8 },
	{ 0x0A, "SAML22G18A", 256, 32 },
	{ 0x0B, "SAML22G17A", 128, 16 },
	{ 0x0C, "SAML22G16A", 64, 8 },
};

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/* Known SAMC20 parts. */
static const struct samd_part samc20_parts[] = {
	{ 0x00, "SAMC20J18A", 256, 32 },
	{ 0x01, "SAMC20J17A", 128, 16 },
	{ 0x02, "SAMC20J16A", 64, 8 },
	{ 0x03, "SAMC20J15A", 32, 4 },
	{ 0x05, "SAMC20G18A", 256, 32 },
	{ 0x06, "SAMC20G17A", 128, 16 },
	{ 0x07, "SAMC20G16A", 64, 8 },
	{ 0x08, "SAMC20G15A", 32, 4 },
	{ 0x0A, "SAMC20E18A", 256, 32 },
	{ 0x0B, "SAMC20E17A", 128, 16 },
	{ 0x0C, "SAMC20E16A", 64, 8 },
	{ 0x0D, "SAMC20E15A", 32, 4 },
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	{ 0x20, "SAMC20N18A", 256, 32 },
	{ 0x21, "SAMC20N17A", 128, 16 },
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};

/* Known SAMC21 parts. */
static const struct samd_part samc21_parts[] = {
	{ 0x00, "SAMC21J18A", 256, 32 },
	{ 0x01, "SAMC21J17A", 128, 16 },
	{ 0x02, "SAMC21J16A", 64, 8 },
	{ 0x03, "SAMC21J15A", 32, 4 },
	{ 0x05, "SAMC21G18A", 256, 32 },
	{ 0x06, "SAMC21G17A", 128, 16 },
	{ 0x07, "SAMC21G16A", 64, 8 },
	{ 0x08, "SAMC21G15A", 32, 4 },
	{ 0x0A, "SAMC21E18A", 256, 32 },
	{ 0x0B, "SAMC21E17A", 128, 16 },
	{ 0x0C, "SAMC21E16A", 64, 8 },
	{ 0x0D, "SAMC21E15A", 32, 4 },
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	{ 0x20, "SAMC21N18A", 256, 32 },
	{ 0x21, "SAMC21N17A", 128, 16 },
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};

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/* Each family of parts contains a parts table in the DEVSEL field of DID.  The
 * processor ID, family ID, and series ID are used to determine which exact
 * family this is and then we can use the corresponding table. */
struct samd_family {
	uint8_t processor;
	uint8_t family;
	uint8_t series;
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	const struct samd_part *parts;
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	size_t num_parts;
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	uint64_t nvm_userrow_res_mask; /* protect bits which are reserved, 0 -> protect */
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};

/* Known SAMD families */
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static const struct samd_family samd_families[] = {
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	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
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		samd20_parts, ARRAY_SIZE(samd20_parts),
		(uint64_t)0xFFFF01FFFE01FF77 },
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	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
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		samd21_parts, ARRAY_SIZE(samd21_parts),
		(uint64_t)0xFFFF01FFFE01FF77 },
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	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_09,
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		samd09_parts, ARRAY_SIZE(samd09_parts),
		(uint64_t)0xFFFF01FFFE01FF77 },
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	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
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		samd10_parts, ARRAY_SIZE(samd10_parts),
		(uint64_t)0xFFFF01FFFE01FF77 },
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	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
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		samd11_parts, ARRAY_SIZE(samd11_parts),
		(uint64_t)0xFFFF01FFFE01FF77 },
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	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
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		saml21_parts, ARRAY_SIZE(saml21_parts),
		(uint64_t)0xFFFF03FFFC01FF77 },
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	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_22,
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		saml22_parts, ARRAY_SIZE(saml22_parts),
		(uint64_t)0xFFFF03FFFC01FF77 },
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	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
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		samc20_parts, ARRAY_SIZE(samc20_parts),
		(uint64_t)0xFFFF03FFFC01FF77 },
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	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
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		samc21_parts, ARRAY_SIZE(samc21_parts),
		(uint64_t)0xFFFF03FFFC01FF77 },
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};

struct samd_info {
	uint32_t page_size;
	int num_pages;
	int sector_size;
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	int prot_block_size;
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	bool probed;
	struct target *target;
};


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/**
 * Gives the family structure to specific device id.
 * @param id The id of the device.
 * @return On failure NULL, otherwise a pointer to the structure.
 */
static const struct samd_family *samd_find_family(uint32_t id)
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{
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	uint8_t processor = SAMD_GET_PROCESSOR(id);
	uint8_t family = SAMD_GET_FAMILY(id);
	uint8_t series = SAMD_GET_SERIES(id);
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	for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
		if (samd_families[i].processor == processor &&
			samd_families[i].series == series &&
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			samd_families[i].family == family)
			return &samd_families[i];
	}

	return NULL;
}

/**
 * Gives the part structure to specific device id.
 * @param id The id of the device.
 * @return On failure NULL, otherwise a pointer to the structure.
 */
static const struct samd_part *samd_find_part(uint32_t id)
{
	uint8_t devsel = SAMD_GET_DEVSEL(id);
	const struct samd_family *family = samd_find_family(id);
	if (family == NULL)
		return NULL;

	for (unsigned i = 0; i < family->num_parts; i++) {
		if (family->parts[i].id == devsel)
			return &family->parts[i];
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	}

	return NULL;
}

static int samd_protect_check(struct flash_bank *bank)
{
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	int res, prot_block;
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	uint16_t lock;

	res = target_read_u16(bank->target,
			SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
	if (res != ERROR_OK)
		return res;

	/* Lock bits are active-low */
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	for (prot_block = 0; prot_block < bank->num_prot_blocks; prot_block++)
		bank->prot_blocks[prot_block].is_protected = !(lock & (1u<<prot_block));
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	return ERROR_OK;
}

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static int samd_get_flash_page_info(struct target *target,
		uint32_t *sizep, int *nump)
{
	int res;
	uint32_t param;

	res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, &param);
	if (res == ERROR_OK) {
		/* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
		 * so 0 is 8KB and 7 is 1024KB. */
		if (sizep)
			*sizep = (8 << ((param >> 16) & 0x7));
		/* The NVMP field (bits 15:0) indicates the total number of pages */
		if (nump)
			*nump = param & 0xFFFF;
	} else {
		LOG_ERROR("Couldn't read NVM Parameters register");
	}

	return res;
}

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static int samd_probe(struct flash_bank *bank)
{
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	uint32_t id;
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	int res;
	struct samd_info *chip = (struct samd_info *)bank->driver_priv;
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	const struct samd_part *part;
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	if (chip->probed)
		return ERROR_OK;

	res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
	if (res != ERROR_OK) {
		LOG_ERROR("Couldn't read Device ID register");
		return res;
	}

	part = samd_find_part(id);
	if (part == NULL) {
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		LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32, id);
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		return ERROR_FAIL;
	}

	bank->size = part->flash_kb * 1024;

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	res = samd_get_flash_page_info(bank->target, &chip->page_size,
			&chip->num_pages);
	if (res != ERROR_OK) {
		LOG_ERROR("Couldn't determine Flash page size");
		return res;
	}
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	/* Sanity check: the total flash size in the DSU should match the page size
	 * multiplied by the number of pages. */
	if (bank->size != chip->num_pages * chip->page_size) {
		LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
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				"Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
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				part->flash_kb, chip->num_pages, chip->page_size);
	}

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	/* Erase granularity = 1 row = 4 pages */
	chip->sector_size = chip->page_size * 4;

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	/* Allocate the sector table */
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	bank->num_sectors = chip->num_pages / 4;
	bank->sectors = alloc_block_array(0, chip->sector_size, bank->num_sectors);
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	if (!bank->sectors)
		return ERROR_FAIL;

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	/* 16 protection blocks per device */
	chip->prot_block_size = bank->size / SAMD_NUM_PROT_BLOCKS;

	/* Allocate the table of protection blocks */
	bank->num_prot_blocks = SAMD_NUM_PROT_BLOCKS;
	bank->prot_blocks = alloc_block_array(0, chip->prot_block_size, bank->num_prot_blocks);
	if (!bank->prot_blocks)
		return ERROR_FAIL;
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	samd_protect_check(bank);

	/* Done */
	chip->probed = true;

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	LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
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			part->flash_kb, part->ram_kb);

	return ERROR_OK;
}

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static int samd_check_error(struct target *target)
490
{
491
	int ret, ret2;
492 493
	uint16_t status;

494
	ret = target_read_u16(target,
495 496 497
			SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
	if (ret != ERROR_OK) {
		LOG_ERROR("Can't read NVM status");
498
		return ret;
499 500
	}

501 502
	if ((status & 0x001C) == 0)
		return ERROR_OK;
503

504 505 506 507 508 509 510 511 512 513 514 515 516
	if (status & (1 << 4)) { /* NVME */
		LOG_ERROR("SAMD: NVM Error");
		ret = ERROR_FLASH_OPERATION_FAILED;
	}

	if (status & (1 << 3)) { /* LOCKE */
		LOG_ERROR("SAMD: NVM lock error");
		ret = ERROR_FLASH_PROTECTED;
	}

	if (status & (1 << 2)) { /* PROGE */
		LOG_ERROR("SAMD: NVM programming error");
		ret = ERROR_FLASH_OPER_UNSUPPORTED;
517 518 519
	}

	/* Clear the error conditions by writing a one to them */
520
	ret2 = target_write_u16(target,
521
			SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
522
	if (ret2 != ERROR_OK)
523 524
		LOG_ERROR("Can't clear NVM error conditions");

525
	return ret;
526 527
}

528 529
static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
{
530 531
	int res;

532 533 534 535 536 537
	if (target->state != TARGET_HALTED) {
		LOG_ERROR("Target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}

	/* Issue the NVM command */
538
	res = target_write_u16(target,
539 540 541 542 543
			SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
	if (res != ERROR_OK)
		return res;

	/* Check to see if the NVM command resulted in an error condition. */
544
	return samd_check_error(target);
545 546
}

547 548 549 550 551 552
/**
 * Erases a flash-row at the given address.
 * @param target Pointer to the target structure.
 * @param address The address of the row.
 * @return On success ERROR_OK, on failure an errorcode.
 */
553
static int samd_erase_row(struct target *target, uint32_t address)
554 555 556
{
	int res;

557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573
	/* Set an address contained in the row to be erased */
	res = target_write_u32(target,
			SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);

	/* Issue the Erase Row command to erase that row. */
	if (res == ERROR_OK)
		res = samd_issue_nvmctrl_command(target,
				address == SAMD_USER_ROW ? SAMD_NVM_CMD_EAR : SAMD_NVM_CMD_ER);

	if (res != ERROR_OK)  {
		LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
		return ERROR_FAIL;
	}

	return ERROR_OK;
}

574 575 576 577 578 579 580
/**
 * Returns the bitmask of reserved bits in register.
 * @param target Pointer to the target structure.
 * @param mask Bitmask, 0 -> value stays untouched.
 * @return On success ERROR_OK, on failure an errorcode.
 */
static int samd_get_reservedmask(struct target *target, uint64_t *mask)
581
{
582 583 584 585 586 587 588 589 590 591 592 593 594
	int res;
	/* Get the devicetype */
	uint32_t id;
	res = target_read_u32(target, SAMD_DSU + SAMD_DSU_DID, &id);
	if (res != ERROR_OK) {
		LOG_ERROR("Couldn't read Device ID register");
		return res;
	}
	const struct samd_family *family;
	family = samd_find_family(id);
	if (family == NULL) {
		LOG_ERROR("Couldn't determine device family");
		return ERROR_FAIL;
595
	}
596 597 598
	*mask = family->nvm_userrow_res_mask;
	return ERROR_OK;
}
599

600 601 602 603 604 605 606 607 608 609 610
static int read_userrow(struct target *target, uint64_t *userrow)
{
	int res;
	uint8_t buffer[8];

	res = target_read_memory(target, SAMD_USER_ROW, 4, 2, buffer);
	if (res != ERROR_OK)
		return res;

	*userrow = target_buffer_get_u64(target, buffer);
	return ERROR_OK;
611 612
}

613 614 615 616 617 618 619 620 621 622 623 624
/**
 * Modify the contents of the User Row in Flash. The User Row itself
 * has a size of one page and contains a combination of "fuses" and
 * calibration data. Bits which have a value of zero in the mask will
 * not be changed. Up to now devices only use the first 64 bits.
 * @param target Pointer to the target structure.
 * @param value_input The value to write.
 * @param value_mask Bitmask, 0 -> value stays untouched.
 * @return On success ERROR_OK, on failure an errorcode.
 */
static int samd_modify_user_row_masked(struct target *target,
		uint64_t value_input, uint64_t value_mask)
625 626
{
	int res;
627 628
	uint32_t nvm_ctrlb;
	bool manual_wp = true;
629 630 631 632 633 634 635 636 637 638

	/* Retrieve the MCU's page size, in bytes. This is also the size of the
	 * entire User Row. */
	uint32_t page_size;
	res = samd_get_flash_page_info(target, &page_size, NULL);
	if (res != ERROR_OK) {
		LOG_ERROR("Couldn't determine Flash page size");
		return res;
	}

639 640 641
	/* Make sure the size is sane. */
	assert(page_size <= SAMD_PAGE_SIZE_MAX &&
		page_size >= sizeof(value_input));
642

643
	uint8_t buf[SAMD_PAGE_SIZE_MAX];
644 645
	/* Read the user row (comprising one page) by words. */
	res = target_read_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
646
	if (res != ERROR_OK)
647 648 649 650 651 652 653
		return res;

	uint64_t value_device;
	res = read_userrow(target, &value_device);
	if (res != ERROR_OK)
		return res;
	uint64_t value_new = (value_input & value_mask) | (value_device & ~value_mask);
654 655 656 657

	/* We will need to erase before writing if the new value needs a '1' in any
	 * position for which the current value had a '0'.  Otherwise we can avoid
	 * erasing. */
658
	if ((~value_device) & value_new) {
659 660 661
		res = samd_erase_row(target, SAMD_USER_ROW);
		if (res != ERROR_OK) {
			LOG_ERROR("Couldn't erase user row");
662
			return res;
663 664 665 666
		}
	}

	/* Modify */
667
	target_buffer_set_u64(target, buf, value_new);
668

669
	/* Write the page buffer back out to the target. */
670 671
	res = target_write_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
	if (res != ERROR_OK)
672
		return res;
673

674 675 676 677 678 679 680 681
	/* Check if we need to do manual page write commands */
	res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
	if (res == ERROR_OK)
		manual_wp = (nvm_ctrlb & SAMD_NVM_CTRLB_MANW) != 0;
	else {
		LOG_ERROR("Read of NVM register CTRKB failed.");
		return ERROR_FAIL;
	}
682 683 684 685 686
	if (manual_wp) {
		/* Trigger flash write */
		res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_WAP);
	} else {
		res = samd_check_error(target);
687 688 689 690 691
	}

	return res;
}

692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710
/**
 * Modifies the user row register to the given value.
 * @param target Pointer to the target structure.
 * @param value The value to write.
 * @param startb The bit-offset by which the given value is shifted.
 * @param endb The bit-offset of the last bit in value to write.
 * @return On success ERROR_OK, on failure an errorcode.
 */
static int samd_modify_user_row(struct target *target, uint64_t value,
		uint8_t startb, uint8_t endb)
{
	uint64_t mask = 0;
	int i;
	for (i = startb ; i <= endb ; i++)
		mask |= ((uint64_t)1) << i;

	return samd_modify_user_row_masked(target, value << startb, mask);
}

711
static int samd_protect(struct flash_bank *bank, int set, int first_prot_bl, int last_prot_bl)
712
{
713 714
	int res = ERROR_OK;
	int prot_block;
715 716 717 718 719 720 721 722 723

	/* We can issue lock/unlock region commands with the target running but
	 * the settings won't persist unless we're able to modify the LOCK regions
	 * and that requires the target to be halted. */
	if (bank->target->state != TARGET_HALTED) {
		LOG_ERROR("Target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}

724 725 726
	for (prot_block = first_prot_bl; prot_block <= last_prot_bl; prot_block++) {
		if (set != bank->prot_blocks[prot_block].is_protected) {
			/* Load an address that is within this protection block (we use offset 0) */
727 728
			res = target_write_u32(bank->target,
							SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
729
							bank->prot_blocks[prot_block].offset >> 1);
730 731 732
			if (res != ERROR_OK)
				goto exit;

733
			/* Tell the controller to lock that block */
734 735 736 737 738 739 740
			res = samd_issue_nvmctrl_command(bank->target,
					set ? SAMD_NVM_CMD_LR : SAMD_NVM_CMD_UR);
			if (res != ERROR_OK)
				goto exit;
		}
	}

741 742
	/* We've now applied our changes, however they will be undone by the next
	 * reset unless we also apply them to the LOCK bits in the User Page.  The
743
	 * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
744 745
	 * corresponding to Sector 15.  A '1' means unlocked and a '0' means
	 * locked.  See Table 9-3 in the SAMD20 datasheet for more details. */
746

747 748
	res = samd_modify_user_row(bank->target,
			set ? (uint64_t)0 : (uint64_t)UINT64_MAX,
749
			48 + first_prot_bl, 48 + last_prot_bl);
750 751
	if (res != ERROR_OK)
		LOG_WARNING("SAMD: protect settings were not made persistent!");
752

753
	res = ERROR_OK;
754

755 756
exit:
	samd_protect_check(bank);
757

758
	return res;
759 760
}

761
static int samd_erase(struct flash_bank *bank, int first_sect, int last_sect)
762
{
763
	int res, s;
764 765 766 767 768 769 770 771 772 773 774 775 776 777
	struct samd_info *chip = (struct samd_info *)bank->driver_priv;

	if (bank->target->state != TARGET_HALTED) {
		LOG_ERROR("Target not halted");

		return ERROR_TARGET_NOT_HALTED;
	}

	if (!chip->probed) {
		if (samd_probe(bank) != ERROR_OK)
			return ERROR_FLASH_BANK_NOT_PROBED;
	}

	/* For each sector to be erased */
778 779 780 781 782
	for (s = first_sect; s <= last_sect; s++) {
		res = samd_erase_row(bank->target, bank->sectors[s].offset);
		if (res != ERROR_OK) {
			LOG_ERROR("SAMD: failed to erase sector %d at 0x%08" PRIx32, s, bank->sectors[s].offset);
			return res;
783
		}
784 785
	}

786
	return ERROR_OK;
787 788 789
}


790
static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
791 792 793
		uint32_t offset, uint32_t count)
{
	int res;
794
	uint32_t nvm_ctrlb;
795
	uint32_t address;
796 797 798
	uint32_t pg_offset;
	uint32_t nb;
	uint32_t nw;
799
	struct samd_info *chip = (struct samd_info *)bank->driver_priv;
800 801
	uint8_t *pb = NULL;
	bool manual_wp;
802 803 804 805 806 807 808 809 810 811 812

	if (bank->target->state != TARGET_HALTED) {
		LOG_ERROR("Target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}

	if (!chip->probed) {
		if (samd_probe(bank) != ERROR_OK)
			return ERROR_FLASH_BANK_NOT_PROBED;
	}

813 814 815 816 817 818 819
	/* Check if we need to do manual page write commands */
	res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);

	if (res != ERROR_OK)
		return res;

	if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
820
		manual_wp = true;
821
	else
822
		manual_wp = false;
823

824 825 826 827 828
	res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
	if (res != ERROR_OK) {
		LOG_ERROR("%s: %d", __func__, __LINE__);
		return res;
	}
829

830 831 832
	while (count) {
		nb = chip->page_size - offset % chip->page_size;
		if (count < nb)
833 834
			nb = count;

835 836
		address = bank->base + offset;
		pg_offset = offset % chip->page_size;
837

838 839 840 841 842 843 844
		if (offset % 4 || (offset + nb) % 4) {
			/* Either start or end of write is not word aligned */
			if (!pb) {
				pb = malloc(chip->page_size);
				if (!pb)
					return ERROR_FAIL;
			}
845

846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873
			/* Set temporary page buffer to 0xff and overwrite the relevant part */
			memset(pb, 0xff, chip->page_size);
			memcpy(pb + pg_offset, buffer, nb);

			/* Align start address to a word boundary */
			address -= offset % 4;
			pg_offset -= offset % 4;
			assert(pg_offset % 4 == 0);

			/* Extend length to whole words */
			nw = (nb + offset % 4 + 3) / 4;
			assert(pg_offset + 4 * nw <= chip->page_size);

			/* Now we have original data extended by 0xff bytes
			 * to the nearest word boundary on both start and end */
			res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
		} else {
			assert(nb % 4 == 0);
			nw = nb / 4;
			assert(pg_offset + 4 * nw <= chip->page_size);

			/* Word aligned data, use direct write from buffer */
			res = target_write_memory(bank->target, address, 4, nw, buffer);
		}
		if (res != ERROR_OK) {
			LOG_ERROR("%s: %d", __func__, __LINE__);
			goto free_pb;
		}
874

875 876 877 878 879 880
		/* Devices with errata 13134 have automatic page write enabled by default
		 * For other devices issue a write page CMD to the NVM
		 * If the page has not been written up to the last word
		 * then issue CMD_WP always */
		if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
			res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
881 882 883
		} else {
			/* Access through AHB is stalled while flash is being programmed */
			usleep(200);
884

885 886
			res = samd_check_error(bank->target);
		}
887

888
		if (res != ERROR_OK) {
889 890
			LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
			goto free_pb;
891
		}
892 893 894 895 896

		/* We're done with the page contents */
		count -= nb;
		offset += nb;
		buffer += nb;
897 898
	}

899 900 901 902 903
free_pb:
	if (pb)
		free(pb);

	return res;
904 905 906 907 908
}

FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
{
	if (bank->base != SAMD_FLASH) {
909 910
		LOG_ERROR("Address " TARGET_ADDR_FMT
				" invalid bank address (try 0x%08" PRIx32
911 912 913 914 915
				"[at91samd series] )",
				bank->base, SAMD_FLASH);
		return ERROR_FAIL;
	}

916 917 918 919 920 921 922 923 924 925 926 927
	struct samd_info *chip;
	chip = calloc(1, sizeof(*chip));
	if (!chip) {
		LOG_ERROR("No memory for flash bank chip info");
		return ERROR_FAIL;
	}

	chip->target = bank->target;
	chip->probed = false;

	bank->driver_priv = chip;

928 929 930 931 932 933 934 935
	return ERROR_OK;
}

COMMAND_HANDLER(samd_handle_info_command)
{
	return ERROR_OK;
}

936 937 938
COMMAND_HANDLER(samd_handle_chip_erase_command)
{
	struct target *target = get_current_target(CMD_CTX);
939
	int res = ERROR_FAIL;
940 941 942 943

	if (target) {
		/* Enable access to the DSU by disabling the write protect bit */
		target_write_u32(target, SAMD_PAC1, (1<<1));
944 945
		/* intentionally without error checking - not accessible on secured chip */

946 947
		/* Tell the DSU to perform a full chip erase.  It takes about 240ms to
		 * perform the erase. */
948 949 950 951 952
		res = target_write_u8(target, SAMD_DSU + SAMD_DSU_CTRL_EXT, (1<<4));
		if (res == ERROR_OK)
			command_print(CMD_CTX, "chip erase started");
		else
			command_print(CMD_CTX, "write to DSU CTRL failed");
953 954
	}

955
	return res;
956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985
}

COMMAND_HANDLER(samd_handle_set_security_command)
{
	int res = ERROR_OK;
	struct target *target = get_current_target(CMD_CTX);

	if (CMD_ARGC < 1 || (CMD_ARGC >= 1 && (strcmp(CMD_ARGV[0], "enable")))) {
		command_print(CMD_CTX, "supply the \"enable\" argument to proceed.");
		return ERROR_COMMAND_SYNTAX_ERROR;
	}

	if (target) {
		if (target->state != TARGET_HALTED) {
			LOG_ERROR("Target not halted");
			return ERROR_TARGET_NOT_HALTED;
		}

		res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_SSB);

		/* Check (and clear) error conditions */
		if (res == ERROR_OK)
			command_print(CMD_CTX, "chip secured on next power-cycle");
		else
			command_print(CMD_CTX, "failed to secure chip");
	}

	return res;
}

986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037
COMMAND_HANDLER(samd_handle_eeprom_command)
{
	int res = ERROR_OK;
	struct target *target = get_current_target(CMD_CTX);

	if (target) {
		if (target->state != TARGET_HALTED) {
			LOG_ERROR("Target not halted");
			return ERROR_TARGET_NOT_HALTED;
		}

		if (CMD_ARGC >= 1) {
			int val = atoi(CMD_ARGV[0]);
			uint32_t code;

			if (val == 0)
				code = 7;
			else {
				/* Try to match size in bytes with corresponding size code */
				for (code = 0; code <= 6; code++) {
					if (val == (2 << (13 - code)))
						break;
				}

				if (code > 6) {
					command_print(CMD_CTX, "Invalid EEPROM size.  Please see "
							"datasheet for a list valid sizes.");
					return ERROR_COMMAND_SYNTAX_ERROR;
				}
			}

			res = samd_modify_user_row(target, code, 4, 6);
		} else {
			uint16_t val;
			res = target_read_u16(target, SAMD_USER_ROW, &val);
			if (res == ERROR_OK) {
				uint32_t size = ((val >> 4) & 0x7); /* grab size code */

				if (size == 0x7)
					command_print(CMD_CTX, "EEPROM is disabled");
				else {
					/* Otherwise, 6 is 256B, 0 is 16KB */
					command_print(CMD_CTX, "EEPROM size is %u bytes",
							(2 << (13 - size)));
				}
			}
		}
	}

	return res;
}

1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114
static COMMAND_HELPER(get_u64_from_hexarg, unsigned int num, uint64_t *value)
{
	if (num >= CMD_ARGC) {
		command_print(CMD_CTX, "Too few Arguments.");
		return ERROR_COMMAND_SYNTAX_ERROR;
	}

	if (strlen(CMD_ARGV[num]) >= 3 &&
		CMD_ARGV[num][0] == '0' &&
		CMD_ARGV[num][1] == 'x') {
		char *check = NULL;
		*value = strtoull(&(CMD_ARGV[num][2]), &check, 16);
		if ((value == 0 && errno == ERANGE) ||
			check == NULL || *check != 0) {
			command_print(CMD_CTX, "Invalid 64-bit hex value in argument %d.",
				num + 1);
			return ERROR_COMMAND_SYNTAX_ERROR;
		}
	} else {
		command_print(CMD_CTX, "Argument %d needs to be a hex value.", num + 1);
		return ERROR_COMMAND_SYNTAX_ERROR;
	}
	return ERROR_OK;
}

COMMAND_HANDLER(samd_handle_nvmuserrow_command)
{
	int res = ERROR_OK;
	struct target *target = get_current_target(CMD_CTX);

	if (target) {
		if (CMD_ARGC > 2) {
			command_print(CMD_CTX, "Too much Arguments given.");
			return ERROR_COMMAND_SYNTAX_ERROR;
		}

		if (CMD_ARGC > 0) {
			if (target->state != TARGET_HALTED) {
				LOG_ERROR("Target not halted.");
				return ERROR_TARGET_NOT_HALTED;
			}

			uint64_t mask;
			res = samd_get_reservedmask(target, &mask);
			if (res != ERROR_OK) {
				LOG_ERROR("Couldn't determine the mask for reserved bits.");
				return ERROR_FAIL;
			}
			mask &= NVMUSERROW_LOCKBIT_MASK;

			uint64_t value;
			res = CALL_COMMAND_HANDLER(get_u64_from_hexarg, 0, &value);
			if (res != ERROR_OK)
				return res;
			if (CMD_ARGC == 2) {
				uint64_t mask_temp;
				res = CALL_COMMAND_HANDLER(get_u64_from_hexarg, 1, &mask_temp);
				if (res != ERROR_OK)
					return res;
				mask &= mask_temp;
			}
			res = samd_modify_user_row_masked(target, value, mask);
			if (res != ERROR_OK)
				return res;
		}

		/* read register */
		uint64_t value;
		res = read_userrow(target, &value);
		if (res == ERROR_OK)
			command_print(CMD_CTX, "NVMUSERROW: 0x%016"PRIX64, value);
		else
			LOG_ERROR("NVMUSERROW could not be read.");
	}
	return res;
}

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COMMAND_HANDLER(samd_handle_bootloader_command)
{
	int res = ERROR_OK;
	struct target *target = get_current_target(CMD_CTX);

	if (target) {
		if (target->state != TARGET_HALTED) {
			LOG_ERROR("Target not halted");
			return ERROR_TARGET_NOT_HALTED;
		}

		/* Retrieve the MCU's page size, in bytes. */
		uint32_t page_size;
		res = samd_get_flash_page_info(target, &page_size, NULL);
		if (res != ERROR_OK) {
			LOG_ERROR("Couldn't determine Flash page size");
			return res;
		}

		if (CMD_ARGC >= 1) {
			int val = atoi(CMD_ARGV[0]);
			uint32_t code;

			if (val == 0)
				code = 7;
			else {
				/* Try to match size in bytes with corresponding size code */
				for (code = 0; code <= 6; code++) {
					if ((unsigned int)val == (2UL << (8UL - code)) * page_size)
						break;
				}

				if (code > 6) {
					command_print(CMD_CTX, "Invalid bootloader size.  Please "
							"see datasheet for a list valid sizes.");
					return ERROR_COMMAND_SYNTAX_ERROR;
				}

			}

			res = samd_modify_user_row(target, code, 0, 2);
		} else {
			uint16_t val;
			res = target_read_u16(target, SAMD_USER_ROW, &val);
			if (res == ERROR_OK) {
				uint32_t size = (val & 0x7); /* grab size code */
				uint32_t nb;

				if (size == 0x7)
					nb = 0;
				else
					nb = (2 << (8 - size)) * page_size;

				/* There are 4 pages per row */
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				command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
					   nb, (uint32_t)(nb / (page_size * 4)));
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			}
		}
	}

	return res;
}

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COMMAND_HANDLER(samd_handle_reset_deassert)
{
	struct target *target = get_current_target(CMD_CTX);
	int retval = ERROR_OK;
	enum reset_types jtag_reset_config = jtag_get_reset_config();

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	/* If the target has been unresponsive before, try to re-establish
	 * communication now - CPU is held in reset by DSU, DAP is working */
	if (!target_was_examined(target))
		target_examine_one(target);
	target_poll(target);

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	/* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
	 * so we just release reset held by DSU
	 *
	 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
	 *
	 * After vectreset DSU release is not needed however makes no harm
	 */
	if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
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		retval = target_write_u32(target, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
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		if (retval == ERROR_OK)
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			retval = target_write_u32(target, DCB_DEMCR,
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				TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
		/* do not return on error here, releasing DSU reset is more important */
	}

	/* clear CPU Reset Phase Extension bit */
	int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
	if (retval2 != ERROR_OK)
		return retval2;

	return retval;
}

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static const struct command_registration at91samd_exec_command_handlers[] = {