at91sam4.c 78.5 KB
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/***************************************************************************
 *   Copyright (C) 2009 by Duane Ellis                                     *
 *   openocd@duaneellis.com                                                *
 *                                                                         *
 *   Copyright (C) 2010 by Olaf Lüke (at91sam3s* support)                  *
 *   olaf@uni-paderborn.de                                                 *
 *                                                                         *
 *   Copyright (C) 2011 by Olivier Schonken, Jim Norris                    *
 *   (at91sam3x* & at91sam4 support)*                                      *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
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 *   it under the terms of the GNU General Public License as published by  *
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 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
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 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
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 *                                                                         *
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 *   You should have received a copy of the GNU General Public License     *
 *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
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****************************************************************************/

/* Some of the the lower level code was based on code supplied by
 * ATMEL under this copyright. */

/* BEGIN ATMEL COPYRIGHT */
/* ----------------------------------------------------------------------------
 *         ATMEL Microcontroller Software Support
 * ----------------------------------------------------------------------------
 * Copyright (c) 2009, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */
/* END ATMEL COPYRIGHT */

#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "imp.h"
#include <helper/time_support.h>

#define REG_NAME_WIDTH  (12)

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/* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
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#define FLASH_BANK_BASE_S   0x00400000
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#define FLASH_BANK_BASE_C   0x01000000
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/* at91sam4sd series (two one flash banks), first bank address */
#define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
/* at91sam4sd16x, second bank address */
#define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
/* at91sam4sd32x, second bank address */
#define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))

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/* at91sam4c32x, first and second bank address */
#define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
#define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))

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#define         AT91C_EFC_FCMD_GETD                 (0x0)	/* (EFC) Get Flash Descriptor */
#define         AT91C_EFC_FCMD_WP                   (0x1)	/* (EFC) Write Page */
#define         AT91C_EFC_FCMD_WPL                  (0x2)	/* (EFC) Write Page and Lock */
#define         AT91C_EFC_FCMD_EWP                  (0x3)	/* (EFC) Erase Page and Write Page */
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#define         AT91C_EFC_FCMD_EWPL                 (0x4)	/* (EFC) Erase Page and Write Page then Lock */
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#define         AT91C_EFC_FCMD_EA                   (0x5)	/* (EFC) Erase All */
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/* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
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/* #define      AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane? */
#define			AT91C_EFC_FCMD_EPA                  (0x7)     /* (EFC) Erase pages */
#define         AT91C_EFC_FCMD_SLB                  (0x8)	/* (EFC) Set Lock Bit */
#define         AT91C_EFC_FCMD_CLB                  (0x9)	/* (EFC) Clear Lock Bit */
#define         AT91C_EFC_FCMD_GLB                  (0xA)	/* (EFC) Get Lock Bit */
#define         AT91C_EFC_FCMD_SFB                  (0xB)	/* (EFC) Set Fuse Bit */
#define         AT91C_EFC_FCMD_CFB                  (0xC)	/* (EFC) Clear Fuse Bit */
#define         AT91C_EFC_FCMD_GFB                  (0xD)	/* (EFC) Get Fuse Bit */
#define         AT91C_EFC_FCMD_STUI                 (0xE)	/* (EFC) Start Read Unique ID */
#define         AT91C_EFC_FCMD_SPUI                 (0xF)	/* (EFC) Stop Read Unique ID */

#define  offset_EFC_FMR   0
#define  offset_EFC_FCR   4
#define  offset_EFC_FSR   8
#define  offset_EFC_FRR   12

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extern const struct flash_driver at91sam4_flash;
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static float _tomhz(uint32_t freq_hz)
{
	float f;

	f = ((float)(freq_hz)) / 1000000.0;
	return f;
}

/* How the chip is configured. */
struct sam4_cfg {
	uint32_t unique_id[4];

	uint32_t slow_freq;
	uint32_t rc_freq;
	uint32_t mainosc_freq;
	uint32_t plla_freq;
	uint32_t mclk_freq;
	uint32_t cpu_freq;
	uint32_t fclk_freq;
	uint32_t pclk0_freq;
	uint32_t pclk1_freq;
	uint32_t pclk2_freq;


#define SAM4_CHIPID_CIDR          (0x400E0740)
	uint32_t CHIPID_CIDR;
#define SAM4_CHIPID_EXID          (0x400E0744)
	uint32_t CHIPID_EXID;

#define SAM4_PMC_BASE             (0x400E0400)
#define SAM4_PMC_SCSR             (SAM4_PMC_BASE + 0x0008)
	uint32_t PMC_SCSR;
#define SAM4_PMC_PCSR             (SAM4_PMC_BASE + 0x0018)
	uint32_t PMC_PCSR;
#define SAM4_CKGR_UCKR            (SAM4_PMC_BASE + 0x001c)
	uint32_t CKGR_UCKR;
#define SAM4_CKGR_MOR             (SAM4_PMC_BASE + 0x0020)
	uint32_t CKGR_MOR;
#define SAM4_CKGR_MCFR            (SAM4_PMC_BASE + 0x0024)
	uint32_t CKGR_MCFR;
#define SAM4_CKGR_PLLAR           (SAM4_PMC_BASE + 0x0028)
	uint32_t CKGR_PLLAR;
#define SAM4_PMC_MCKR             (SAM4_PMC_BASE + 0x0030)
	uint32_t PMC_MCKR;
#define SAM4_PMC_PCK0             (SAM4_PMC_BASE + 0x0040)
	uint32_t PMC_PCK0;
#define SAM4_PMC_PCK1             (SAM4_PMC_BASE + 0x0044)
	uint32_t PMC_PCK1;
#define SAM4_PMC_PCK2             (SAM4_PMC_BASE + 0x0048)
	uint32_t PMC_PCK2;
#define SAM4_PMC_SR               (SAM4_PMC_BASE + 0x0068)
	uint32_t PMC_SR;
#define SAM4_PMC_IMR              (SAM4_PMC_BASE + 0x006c)
	uint32_t PMC_IMR;
#define SAM4_PMC_FSMR             (SAM4_PMC_BASE + 0x0070)
	uint32_t PMC_FSMR;
#define SAM4_PMC_FSPR             (SAM4_PMC_BASE + 0x0074)
	uint32_t PMC_FSPR;
};

struct sam4_bank_private {
	int probed;
	/* DANGER: THERE ARE DRAGONS HERE.. */
	/* NOTE: If you add more 'ghost' pointers */
	/* be aware that you must *manually* update */
	/* these pointers in the function sam4_GetDetails() */
	/* See the comment "Here there be dragons" */

	/* so we can find the chip we belong to */
	struct sam4_chip *pChip;
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	/* so we can find the original bank pointer */
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	struct flash_bank *pBank;
	unsigned bank_number;
	uint32_t controller_address;
	uint32_t base_address;
	uint32_t flash_wait_states;
	bool present;
	unsigned size_bytes;
	unsigned nsectors;
	unsigned sector_size;
	unsigned page_size;
};

struct sam4_chip_details {
	/* THERE ARE DRAGONS HERE.. */
	/* note: If you add pointers here */
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	/* be careful about them as they */
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	/* may need to be updated inside */
	/* the function: "sam4_GetDetails() */
	/* which copy/overwrites the */
	/* 'runtime' copy of this structure */
	uint32_t chipid_cidr;
	const char *name;

	unsigned n_gpnvms;
#define SAM4_N_NVM_BITS 3
	unsigned gpnvm[SAM4_N_NVM_BITS];
	unsigned total_flash_size;
	unsigned total_sram_size;
	unsigned n_banks;
#define SAM4_MAX_FLASH_BANKS 2
	/* these are "initialized" from the global const data */
	struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
};

struct sam4_chip {
	struct sam4_chip *next;
	int probed;

	/* this is "initialized" from the global const structure */
	struct sam4_chip_details details;
	struct target *target;
	struct sam4_cfg cfg;
};


struct sam4_reg_list {
	uint32_t address;  size_t struct_offset; const char *name;
	void (*explain_func)(struct sam4_chip *pInfo);
};

static struct sam4_chip *all_sam4_chips;

static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
{
	struct target *t;
	static struct sam4_chip *p;

	t = get_current_target(cmd_ctx);
	if (!t) {
		command_print(cmd_ctx, "No current target?");
		return NULL;
	}

	p = all_sam4_chips;
	if (!p) {
		/* this should not happen */
		/* the command is not registered until the chip is created? */
		command_print(cmd_ctx, "No SAM4 chips exist?");
		return NULL;
	}

	while (p) {
		if (p->target == t)
			return p;
		p = p->next;
	}
	command_print(cmd_ctx, "Cannot find SAM4 chip?");
	return NULL;
}

/*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
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/*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
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/*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
/*set to the lock region size.  Page erases are used to erase 8KB sections when programming*/

/* these are used to *initialize* the "pChip->details" structure. */
static const struct sam4_chip_details all_sam4_details[] = {
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	/* Start at91sam4c* series */
	/* at91sam4c32e - LQFP144 */
	{
		.chipid_cidr    = 0xA66D0EE0,
		.name           = "at91sam4c32e",
		.total_flash_size     = 2024 * 1024,
		.total_sram_size      = 256 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 2,
/*		.bank[0] = { */
		{
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_C32,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 5,
				.present = 1,
				.size_bytes =  1024 * 1024,
				.nsectors   =  128,
				.sector_size = 8192,
				.page_size   = 512,
			},
/*		.bank[1] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 1,
				.base_address = FLASH_BANK1_BASE_C32,
				.controller_address = 0x400e0c00,
				.flash_wait_states = 5,
				.present = 1,
				.size_bytes =  1024 * 1024,
				.nsectors   =  128,
				.sector_size = 8192,
				.page_size   = 512,
			},
		},
	},
	/* at91sam4c32c - LQFP100 */
	{
		.chipid_cidr    = 0xA64D0EE0,
		.name           = "at91sam4c32c",
		.total_flash_size     = 2024 * 1024,
		.total_sram_size      = 256 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 2,
/*		.bank[0] = { */
		{
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_C32,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 5,
				.present = 1,
				.size_bytes =  1024 * 1024,
				.nsectors   =  128,
				.sector_size = 8192,
				.page_size   = 512,
			},
/*		.bank[1] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 1,
				.base_address = FLASH_BANK1_BASE_C32,
				.controller_address = 0x400e0c00,
				.flash_wait_states = 5,
				.present = 1,
				.size_bytes =  1024 * 1024,
				.nsectors   =  128,
				.sector_size = 8192,
				.page_size   = 512,
			},
		},
	},
	/* at91sam4c16c - LQFP100 */
	{
		.chipid_cidr    = 0xA64C0CE0,
		.name           = "at91sam4c16c",
		.total_flash_size     = 1024 * 1024,
		.total_sram_size      = 128 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_C,
			.controller_address = 0x400e0a00,
			.flash_wait_states = 5,
			.present = 1,
			.size_bytes =  1024 * 1024,
			.nsectors   =  128,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	/* at91sam4c8c - LQFP100 */
	{
		.chipid_cidr    = 0xA64C0AE0,
		.name           = "at91sam4c8c",
		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 128 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_C,
			.controller_address = 0x400e0a00,
			.flash_wait_states = 5,
			.present = 1,
			.size_bytes =  512 * 1024,
			.nsectors   =  64,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	/* at91sam4c4c (rev B) - LQFP100 */
	{
		.chipid_cidr    = 0xA64C0CE5,
		.name           = "at91sam4c4c",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 128 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_C,
			.controller_address = 0x400e0a00,
			.flash_wait_states = 5,
			.present = 1,
			.size_bytes =  256 * 1024,
			.nsectors   =  32,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
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	/* Start at91sam4e* series */
	/*atsam4e16e - LQFP144/LFBGA144*/
	{
		.chipid_cidr    = 0xA3CC0CE0,
		.name           = "at91sam4e16e",
		.total_flash_size     = 1024 * 1024,
		.total_sram_size      = 128 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  1024 * 1024,
			.nsectors   =  128,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},

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	/* Start at91sam4n* series */
	/*atsam4n8a - LQFP48/QFN48*/
	{
		.chipid_cidr    = 0x293B0AE0,
		.name           = "at91sam4n8a",
		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  512 * 1024,
			.nsectors   =  64,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	/*atsam4n8b - LQFP64/QFN64*/
	{
		.chipid_cidr    = 0x294B0AE0,
		.name           = "at91sam4n8b",
		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  512 * 1024,
			.nsectors   =  64,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	/*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
	{
		.chipid_cidr    = 0x295B0AE0,
		.name           = "at91sam4n8c",
		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  512 * 1024,
			.nsectors   =  64,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	/*atsam4n16b - LQFP64/QFN64*/
	{
		.chipid_cidr    = 0x29460CE0,
		.name           = "at91sam4n16b",
		.total_flash_size     = 1024 * 1024,
		.total_sram_size      = 80 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  1024 * 1024,
			.nsectors   =  128,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	/*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
	{
		.chipid_cidr    = 0x29560CE0,
		.name           = "at91sam4n16c",
		.total_flash_size     = 1024 * 1024,
		.total_sram_size      = 80 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  1024 * 1024,
			.nsectors   =  128,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},

651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668
	/* Start at91sam4s* series */
	/*atsam4s16c - LQFP100/BGA100*/
	{
		.chipid_cidr    = 0x28AC0CE0,
		.name           = "at91sam4s16c",
		.total_flash_size     = 1024 * 1024,
		.total_sram_size      = 128 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  1024 * 1024,
			.nsectors   =  128,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
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	/*at91sam4sa16c - TFBGA100/VFBGA100/LQFP100*/
	{
		.chipid_cidr    = 0x28a70ce0,
		.name           = "at91sam4sa16c",
		.total_flash_size     = 1024 * 1024,
		.total_sram_size      = 160 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,

/*		.bank[0] = { */
		{
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
			.flash_wait_states = 5,
			.present = 1,
			.size_bytes =  1024 * 1024,
			.nsectors   =  128,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
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	/*atsam4s16b - LQFP64/QFN64/WLCSP64*/
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	{
		.chipid_cidr    = 0x289C0CE0,
		.name           = "at91sam4s16b",
		.total_flash_size     = 1024 * 1024,
		.total_sram_size      = 128 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  1024 * 1024,
			.nsectors   =  128,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
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	/*atsam4sa16b - LQFP64/QFN64*/
	{
		.chipid_cidr    = 0x28970CE0,
		.name           = "at91sam4sa16b",
		.total_flash_size     = 1024 * 1024,
		.total_sram_size      = 160 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  1024 * 1024,
			.nsectors   =  128,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
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	/*atsam4s16a - LQFP48/QFN48*/
	{
		.chipid_cidr    = 0x288C0CE0,
		.name           = "at91sam4s16a",
		.total_flash_size     = 1024 * 1024,
		.total_sram_size      = 128 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  1024 * 1024,
			.nsectors   =  128,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	/*atsam4s8c - LQFP100/BGA100*/
	{
		.chipid_cidr    = 0x28AC0AE0,
		.name           = "at91sam4s8c",
		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 128 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  512 * 1024,
			.nsectors   =  64,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
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	/*atsam4s8b - LQFP64/QFN64/WLCSP64*/
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	{
		.chipid_cidr    = 0x289C0AE0,
		.name           = "at91sam4s8b",
		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 128 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  512 * 1024,
			.nsectors   =  64,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	/*atsam4s8a - LQFP48/BGA48*/
	{
		.chipid_cidr    = 0x288C0AE0,
		.name           = "at91sam4s8a",
		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 128 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  512 * 1024,
			.nsectors   =  64,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
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	/*atsam4s4c - LQFP100/BGA100*/
	{
		.chipid_cidr    = 0x28ab09e0,
		.name           = "at91sam4s4c",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
			.flash_wait_states = 5,
			.present = 1,
			.size_bytes =  256 * 1024,
			.nsectors   =  32,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},

	/*atsam4s4b - LQFP64/QFN64/WLCSP64*/
	{
		.chipid_cidr    = 0x289b09e0,
		.name           = "at91sam4s4b",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
			.flash_wait_states = 5,
			.present = 1,
			.size_bytes =  256 * 1024,
			.nsectors   =  32,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},

	/*atsam4s4a - LQFP48/QFN48*/
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	{
		.chipid_cidr    = 0x288b09e0,
		.name           = "at91sam4s4a",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 5,
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			.present = 1,
			.size_bytes =  256 * 1024,
			.nsectors   =  32,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},

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	/*atsam4s2c - LQFP100/BGA100*/
	{
		.chipid_cidr    = 0x28ab07e0,
		.name           = "at91sam4s2c",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
			.flash_wait_states = 5,
			.present = 1,
			.size_bytes =  128 * 1024,
			.nsectors   =  16,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},

	/*atsam4s2b - LQPF64/QFN64/WLCSP64*/
	{
		.chipid_cidr    = 0x289b07e0,
		.name           = "at91sam4s2b",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
			.flash_wait_states = 5,
			.present = 1,
			.size_bytes =  128 * 1024,
			.nsectors   =  16,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},

	/*atsam4s2a - LQFP48/QFN48*/
	{
		.chipid_cidr    = 0x288b07e0,
		.name           = "at91sam4s2a",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = {*/
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
			.flash_wait_states = 5,
			.present = 1,
			.size_bytes =  128 * 1024,
			.nsectors   =  16,
			.sector_size = 8192,
			.page_size   = 512,
		  },
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},

	/*at91sam4sd32c  - LQFP100/BGA100*/
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	{
		.chipid_cidr    = 0x29a70ee0,
		.name           = "at91sam4sd32c",
		.total_flash_size     = 2048 * 1024,
		.total_sram_size      = 160 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 2,

/*		.bank[0] = { */
		{
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_SD,
				.controller_address = 0x400e0a00,
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				.flash_wait_states = 5,
				.present = 1,
				.size_bytes =  1024 * 1024,
				.nsectors   =  128,
				.sector_size = 8192,
				.page_size   = 512,
			},

/*		.bank[1] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 1,
				.base_address = FLASH_BANK1_BASE_2048K_SD,
				.controller_address = 0x400e0c00,
				.flash_wait_states = 5,
				.present = 1,
				.size_bytes =  1024 * 1024,
				.nsectors   =  128,
				.sector_size = 8192,
				.page_size   = 512,
			},
		},
	},

	/*at91sam4sd32b  - LQFP64/BGA64*/
	{
		.chipid_cidr    = 0x29970ee0,
		.name           = "at91sam4sd32b",
		.total_flash_size     = 2048 * 1024,
		.total_sram_size      = 160 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 2,

/*		.bank[0] = { */
		{
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_SD,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 5,
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				.present = 1,
				.size_bytes =  1024 * 1024,
				.nsectors   =  128,
				.sector_size = 8192,
				.page_size   = 512,
			},

/*		.bank[1] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 1,
				.base_address = FLASH_BANK1_BASE_2048K_SD,
				.controller_address = 0x400e0c00,
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				.flash_wait_states = 5,
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				.present = 1,
				.size_bytes =  1024 * 1024,
				.nsectors   =  128,
				.sector_size = 8192,
				.page_size   = 512,
			},
		},
	},

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	/*at91sam4sd16c - LQFP100/BGA100*/
Jörg Wunsch's avatar
Jörg Wunsch committed
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	{
		.chipid_cidr    = 0x29a70ce0,
		.name           = "at91sam4sd16c",
		.total_flash_size     = 1024 * 1024,
		.total_sram_size      = 160 * 1024,
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		.n_gpnvms       = 3,
		.n_banks        = 2,

/*		.bank[0] = { */
		{
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_SD,
				.controller_address = 0x400e0a00,
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				.flash_wait_states = 5,
				.present = 1,
				.size_bytes =  512 * 1024,
				.nsectors   =  64,
				.sector_size = 8192,
				.page_size   = 512,
			},

/*		.bank[1] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 1,
				.base_address = FLASH_BANK1_BASE_1024K_SD,
				.controller_address = 0x400e0c00,
				.flash_wait_states = 5,
				.present = 1,
				.size_bytes =  512 * 1024,
				.nsectors   =  64,
				.sector_size = 8192,
				.page_size   = 512,
			},
		},
	},

	/*at91sam4sd16b - LQFP64/BGA64*/
	{
		.chipid_cidr    = 0x29970ce0,
		.name           = "at91sam4sd16b",
		.total_flash_size     = 1024 * 1024,
		.total_sram_size      = 160 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 2,

/*		.bank[0] = { */
		{
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_SD,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 5,
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				.present = 1,
				.size_bytes =  512 * 1024,
				.nsectors   =  64,
				.sector_size = 8192,
				.page_size   = 512,
			},

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/*		.bank[1] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 1,
				.base_address = FLASH_BANK1_BASE_1024K_SD,
				.controller_address = 0x400e0c00,
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				.flash_wait_states = 5,
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				.present = 1,
				.size_bytes =  512 * 1024,
				.nsectors   =  64,
				.sector_size = 8192,
				.page_size   = 512,
			},
		},
	},

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	/* atsamg53n19 */
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	{
		.chipid_cidr    = 0x247e0ae0,
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		.name           = "atsamg53n19",
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		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 96 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,

/*		.bank[0] = {*/
		{
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
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				.flash_wait_states = 5,
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				.present = 1,
				.size_bytes =  512 * 1024,
				.nsectors   =  64,
				.sector_size = 8192,
				.page_size   = 512,
			},
/*		.bank[1] = {*/
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		}
	},

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	/* atsamg55g19 */
	{
		.chipid_cidr    = 0x24470ae0,
		.name           = "atsamg55g19",
		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 160 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,

		{
/*			.bank[0] = */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 5,
				.present = 1,
				.size_bytes =  512 * 1024,
				.nsectors   =  64,
				.sector_size = 8192,
				.page_size   = 512,
			},
/*			.bank[1] = */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
		}
	},

	/* atsamg55j19 */
	{
		.chipid_cidr    = 0x24570ae0,
		.name           = "atsamg55j19",
		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 160 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,

		{
/*			.bank[0] = */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 5,
				.present = 1,
				.size_bytes =  512 * 1024,
				.nsectors   =  64,
				.sector_size = 8192,
				.page_size   = 512,
			},
/*			.bank[1] = */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
		}
	},

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	/* terminate */
	{
		.chipid_cidr    = 0,
		.name                   = NULL,
	}
};

/* Globals above */
/***********************************************************************
 **********************************************************************
 **********************************************************************
 **********************************************************************
 **********************************************************************
 **********************************************************************/
/* *ATMEL* style code - from the SAM4 driver code */

/**
 * Get the current status of the EEFC and
 * the value of some status bits (LOCKE, PROGE).
 * @param pPrivate - info about the bank
 * @param v        - result goes here
 */
static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
{
	int r;
	r = target_read_u32(pPrivate->pChip->target,
			pPrivate->controller_address + offset_EFC_FSR,
			v);
	LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
		(unsigned int)(*v),
		((unsigned int)((*v >> 2) & 1)),
		((unsigned int)((*v >> 1) & 1)),
		((unsigned int)((*v >> 0) & 1)));

	return r;
}

/**
 * Get the result of the last executed command.
 * @param pPrivate - info about the bank
 * @param v        - result goes here
 */
static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
{
	int r;
	uint32_t rv;
	r = target_read_u32(pPrivate->pChip->target,
			pPrivate->controller_address + offset_EFC_FRR,
			&rv);
	if (v)
		*v = rv;
	LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
	return r;
}

static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
	unsigned command, unsigned argument)
{
	uint32_t n, v;
	int r;
	int retry;

	retry = 0;
do_retry:

	/* Check command & argument */
	switch (command) {

		case AT91C_EFC_FCMD_WP:
		case AT91C_EFC_FCMD_WPL:
		case AT91C_EFC_FCMD_EWP:
		case AT91C_EFC_FCMD_EWPL:
		/* case AT91C_EFC_FCMD_EPL: */
		case AT91C_EFC_FCMD_EPA:
		case AT91C_EFC_FCMD_SLB:
		case AT91C_EFC_FCMD_CLB:
			n = (pPrivate->size_bytes / pPrivate->page_size);
			if (argument >= n)
				LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
			break;

		case AT91C_EFC_FCMD_SFB:
		case AT91C_EFC_FCMD_CFB:
			if (argument >= pPrivate->pChip->details.n_gpnvms) {
				LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
						pPrivate->pChip->details.n_gpnvms);
			}
			break;

		case AT91C_EFC_FCMD_GETD:
		case AT91C_EFC_FCMD_EA:
		case AT91C_EFC_FCMD_GLB:
		case AT91C_EFC_FCMD_GFB:
		case AT91C_EFC_FCMD_STUI:
		case AT91C_EFC_FCMD_SPUI:
			if (argument != 0)
				LOG_ERROR("Argument is meaningless for cmd: %d", command);
			break;
		default:
			LOG_ERROR("Unknown command %d", command);
			break;
	}

	if (command == AT91C_EFC_FCMD_SPUI) {
		/* this is a very special situation. */
		/* Situation (1) - error/retry - see below */
		/*      And we are being called recursively */
		/* Situation (2) - normal, finished reading unique id */
	} else {
		/* it should be "ready" */
		EFC_GetStatus(pPrivate, &v);
		if (v & 1) {
			/* then it is ready */
			/* we go on */
		} else {
			if (retry) {
				/* we have done this before */
				/* the controller is not responding. */
				LOG_ERROR("flash controller(%d) is not ready! Error",
					pPrivate->bank_number);
				return ERROR_FAIL;
			} else {
				retry++;
				LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
					pPrivate->bank_number);
				/* we do that by issuing the *STOP* command */
				EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
				/* above is recursive, and further recursion is blocked by */
				/* if (command == AT91C_EFC_FCMD_SPUI) above */
				goto do_retry;
			}
		}
	}

	v = (0x5A << 24) | (argument << 8) | command;
	LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
	r = target_write_u32(pPrivate->pBank->target,
			pPrivate->controller_address + offset_EFC_FCR, v);
	if (r != ERROR_OK)
		LOG_DEBUG("Error Write failed");
	return r;
}

/**
 * Performs the given command and wait until its completion (or an error).
 * @param pPrivate - info about the bank
 * @param command  - Command to perform.
 * @param argument - Optional command argument.
 * @param status   - put command status bits here
 */
static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
	unsigned command,
	unsigned argument,
	uint32_t *status)
{

	int r;
	uint32_t v;
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	int64_t ms_now, ms_end;
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	/* default */
	if (status)
		*status = 0;

	r = EFC_StartCommand(pPrivate, command, argument);
	if (r != ERROR_OK)
		return r;

	ms_end = 10000 + timeval_ms();

	do {
		r = EFC_GetStatus(pPrivate, &v);
		if (r != ERROR_OK)
			return r;
		ms_now = timeval_ms();
		if (ms_now > ms_end) {
			/* error */
			LOG_ERROR("Command timeout");
			return ERROR_FAIL;
		}
	} while ((v & 1) == 0);

	/* error bits.. */
	if (status)
		*status = (v & 0x6);
	return ERROR_OK;

}

/**
 * Read the unique ID.
 * @param pPrivate - info about the bank
 * The unique ID is stored in the 'pPrivate' structure.
 */
static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
{
	int r;
	uint32_t v;
	int x;
	/* assume 0 */
	pPrivate->pChip->cfg.unique_id[0] = 0;
	pPrivate->pChip->cfg.unique_id[1] = 0;
	pPrivate->pChip->cfg.unique_id[2] = 0;
	pPrivate->pChip->cfg.unique_id[3] = 0;

	LOG_DEBUG("Begin");
	r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
	if (r < 0)
		return r;

	for (x = 0; x < 4; x++) {
		r = target_read_u32(pPrivate->pChip->target,
				pPrivate->pBank->base + (x * 4),
				&v);
		if (r < 0)
			return r;
		pPrivate->pChip->cfg.unique_id[x] = v;
	}

	r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
	LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
		r,
		(unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
		(unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
		(unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
		(unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
	return r;

}

/**
 * Erases the entire flash.
 * @param pPrivate - the info about the bank.
 */
static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
{
	LOG_DEBUG("Here");
	return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
}

/**
 * Erases the entire flash.
 * @param pPrivate - the info about the bank.
 */
static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
							 int firstPage,
							 int numPages,
							 uint32_t *status)
{
	LOG_DEBUG("Here");
	uint8_t erasePages;
	switch (numPages)	{
		case 4:
			erasePages = 0x00;
			break;
		case 8:
			erasePages = 0x01;
			break;
		case 16:
			erasePages = 0x02;
			break;
		case 32:
			erasePages = 0x03;
			break;
		default:
			erasePages = 0x00;
			break;
	}

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	/* AT91C_EFC_FCMD_EPA
	 * According to the datasheet FARG[15:2] defines the page from which
	 * the erase will start.This page must be modulo 4, 8, 16 or 32
	 * according to the number of pages to erase. FARG[1:0] defines the
	 * number of pages to be erased. Previously (firstpage << 2) was used
	 * to conform to this, seems it should not be shifted...
	 */
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	return EFC_PerformCommand(pPrivate,
		/* send Erase Page */
		AT91C_EFC_FCMD_EPA,
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		(firstPage) | erasePages,
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		status);
}

/**
 * Gets current GPNVM state.
 * @param pPrivate - info about the bank.
 * @param gpnvm    -  GPNVM bit index.
 * @param puthere  - result stored here.
 */
/* ------------------------------------------------------------------------------ */
static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
{
	uint32_t v;
	int r;

	LOG_DEBUG("Here");
	if (pPrivate->bank_number != 0) {
		LOG_ERROR("GPNVM only works with Bank0");
		return ERROR_FAIL;
	}

	if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
		LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
			gpnvm, pPrivate->pChip->details.n_gpnvms);
		return ERROR_FAIL;
	}

	/* Get GPNVMs status */
	r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
	if (r != ERROR_OK) {
		LOG_ERROR("Failed");
		return r;
	}

	r = EFC_GetResult(pPrivate, &v);

	if (puthere) {
		/* Check if GPNVM is set */
		/* get the bit and make it a 0/1 */
		*puthere = (v >> gpnvm) & 1;
	}

	return r;
}

/**
 * Clears the selected GPNVM bit.
 * @param pPrivate info about the bank
 * @param gpnvm GPNVM index.
 * @returns 0 if successful; otherwise returns an error code.
 */
static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
{
	int r;
	unsigned v;

	LOG_DEBUG("Here");
	if (pPrivate->bank_number != 0) {
		LOG_ERROR("GPNVM only works with Bank0");
		return ERROR_FAIL;
	}

	if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
		LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
			gpnvm, pPrivate->pChip->details.n_gpnvms);
		return ERROR_FAIL;
	}

	r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
	if (r != ERROR_OK) {
		LOG_DEBUG("Failed: %d", r);
		return r;
	}
	r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
	LOG_DEBUG("End: %d", r);
	return r;
}

/**
 * Sets the selected GPNVM bit.
 * @param pPrivate info about the bank
 * @param gpnvm GPNVM index.
 */
static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
{
	int r;
	unsigned v;

	if (pPrivate->bank_number != 0) {
		LOG_ERROR("GPNVM only works with Bank0");
		return ERROR_FAIL;
	}

	if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
		LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
			gpnvm, pPrivate->pChip->details.n_gpnvms);
		return ERROR_FAIL;
	}

	r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
	if (r != ERROR_OK)
		return r;
	if (v) {
		/* already set */
		r = ERROR_OK;
	} else {
		/* set it */
		r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
	}
	return r;
}

/**
 * Returns a bit field (at most 64) of locked regions within a page.
 * @param pPrivate info about the bank
 * @param v where to store locked bits
 */
static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
{
	int r;
	LOG_DEBUG("Here");
	r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
	if (r == ERROR_OK)	{
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		EFC_GetResult(pPrivate, v);
		EFC_GetResult(pPrivate, v);
		EFC_GetResult(pPrivate, v);
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		r = EFC_GetResult(pPrivate, v);
	}
	LOG_DEBUG("End: %d", r);
	return r;
}

/**
 * Unlocks all the regions in the given address range.
 * @param pPrivate info about the bank
 * @param start_sector first sector to unlock
 * @param end_sector last (inclusive) to unlock
 */

static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
	unsigned start_sector,
	unsigned end_sector)
{
	int r;
	uint32_t status;
	uint32_t pg;
	uint32_t pages_per_sector;

	pages_per_sector = pPrivate->sector_size / pPrivate->page_size;

	/* Unlock all pages */
	while (start_sector <= end_sector) {
		pg = start_sector * pages_per_sector;

		r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
		if (r != ERROR_OK)
			return r;
		start_sector++;
	}

	return ERROR_OK;
}

/**
 * Locks regions
 * @param pPrivate - info about the bank
 * @param start_sector - first sector to lock
 * @param end_sector   - last sector (inclusive) to lock
 */
static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
	unsigned start_sector,
	unsigned end_sector)
{
	uint32_t status;
	uint32_t pg;
	uint32_t pages_per_sector;
	int r;

	pages_per_sector = pPrivate->sector_size / pPrivate->page_size;

	/* Lock all pages */
	while (start_sector <= end_sector) {
		pg = start_sector * pages_per_sector;

		r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
		if (r != ERROR_OK)
			return r;
		start_sector++;
	}
	return ERROR_OK;
}

/****** END SAM4 CODE ********/

/* begin helpful debug code */
/* print the fieldname, the field value, in dec & hex, and return field value */
static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
	const char *regname,
	uint32_t value,
	unsigned shift,
	unsigned width)
{
	uint32_t v;
	int hwidth, dwidth;


	/* extract the field */
	v = value >> shift;
	v = v & ((1 << width)-1);
	if (width <= 16) {
		hwidth = 4;
		dwidth = 5;
	} else {
		hwidth = 8;
		dwidth = 12;
	}

	/* show the basics */
1899
	LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
1900 1901 1902 1903 1904 1905 1906 1907
		REG_NAME_WIDTH, regname,
		dwidth, v,
		hwidth, v);
	return v;