at91sam3.c 92.1 KB
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/***************************************************************************
 *   Copyright (C) 2009 by Duane Ellis                                     *
 *   openocd@duaneellis.com                                                *
 *                                                                         *
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 *   Copyright (C) 2010 by Olaf Lüke (at91sam3s* support)                  *
 *   olaf@uni-paderborn.de                                                 *
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 *																		   *
 *   Copyright (C) 2011 by Olivier Schonken (at91sam3x* support)           *                                          *
 *                     and Jim Norris                                      *
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 *   This program is free software; you can redistribute it and/or modify  *
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 *   it under the terms of the GNU General Public License as published by  *
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 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
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 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
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 *                                                                         *
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 *   You should have received a copy of the GNU General Public License     *
 *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
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****************************************************************************/

/* Some of the the lower level code was based on code supplied by
 * ATMEL under this copyright. */

/* BEGIN ATMEL COPYRIGHT */
/* ----------------------------------------------------------------------------
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 *         ATMEL Microcontroller Software Support
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 * ----------------------------------------------------------------------------
 * Copyright (c) 2009, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */
/* END ATMEL COPYRIGHT */

#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

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#include "imp.h"
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#include <helper/time_support.h>
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#define REG_NAME_WIDTH  (12)

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/* at91sam3u series (has one or two flash banks) */
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#define FLASH_BANK0_BASE_U   0x00080000
#define FLASH_BANK1_BASE_U   0x00100000
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/* at91sam3s series (has always one flash bank) */
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#define FLASH_BANK_BASE_S   0x00400000
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/* at91sam3sd series (has always two flash banks) */
#define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
#define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))


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/* at91sam3n series (has always one flash bank) */
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#define FLASH_BANK_BASE_N   0x00400000

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/* at91sam3a/x series has two flash banks*/
#define	FLASH_BANK0_BASE_AX			0x00080000
/*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
#define	FLASH_BANK1_BASE_256K_AX	0x000A0000
#define	FLASH_BANK1_BASE_512K_AX	0x000C0000

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#define         AT91C_EFC_FCMD_GETD                 (0x0)	/* (EFC) Get Flash Descriptor */
#define         AT91C_EFC_FCMD_WP                   (0x1)	/* (EFC) Write Page */
#define         AT91C_EFC_FCMD_WPL                  (0x2)	/* (EFC) Write Page and Lock */
#define         AT91C_EFC_FCMD_EWP                  (0x3)	/* (EFC) Erase Page and Write Page */
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#define         AT91C_EFC_FCMD_EWPL                 (0x4)	/* (EFC) Erase Page and Write Page then Lock */
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#define         AT91C_EFC_FCMD_EA                   (0x5)	/* (EFC) Erase All */
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/* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
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/* #define      AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane? */
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/* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
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/* #define      AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase pages? */
#define         AT91C_EFC_FCMD_SLB                  (0x8)	/* (EFC) Set Lock Bit */
#define         AT91C_EFC_FCMD_CLB                  (0x9)	/* (EFC) Clear Lock Bit */
#define         AT91C_EFC_FCMD_GLB                  (0xA)	/* (EFC) Get Lock Bit */
#define         AT91C_EFC_FCMD_SFB                  (0xB)	/* (EFC) Set Fuse Bit */
#define         AT91C_EFC_FCMD_CFB                  (0xC)	/* (EFC) Clear Fuse Bit */
#define         AT91C_EFC_FCMD_GFB                  (0xD)	/* (EFC) Get Fuse Bit */
#define         AT91C_EFC_FCMD_STUI                 (0xE)	/* (EFC) Start Read Unique ID */
#define         AT91C_EFC_FCMD_SPUI                 (0xF)	/* (EFC) Stop Read Unique ID */
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#define  offset_EFC_FMR   0
#define  offset_EFC_FCR   4
#define  offset_EFC_FSR   8
#define  offset_EFC_FRR   12

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extern const struct flash_driver at91sam3_flash;
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static float _tomhz(uint32_t freq_hz)
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{
	float f;

	f = ((float)(freq_hz)) / 1000000.0;
	return f;
}

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/* How the chip is configured. */
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struct sam3_cfg {
	uint32_t unique_id[4];

	uint32_t slow_freq;
	uint32_t rc_freq;
	uint32_t mainosc_freq;
	uint32_t plla_freq;
	uint32_t mclk_freq;
	uint32_t cpu_freq;
	uint32_t fclk_freq;
	uint32_t pclk0_freq;
	uint32_t pclk1_freq;
	uint32_t pclk2_freq;


#define SAM3_CHIPID_CIDR          (0x400E0740)
	uint32_t CHIPID_CIDR;
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#define SAM3_CHIPID_CIDR2         (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
	uint32_t CHIPID_CIDR2;
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#define SAM3_CHIPID_EXID          (0x400E0744)
	uint32_t CHIPID_EXID;
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#define SAM3_CHIPID_EXID2         (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
	uint32_t CHIPID_EXID2;

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#define SAM3_PMC_BASE             (0x400E0400)
#define SAM3_PMC_SCSR             (SAM3_PMC_BASE + 0x0008)
	uint32_t PMC_SCSR;
#define SAM3_PMC_PCSR             (SAM3_PMC_BASE + 0x0018)
	uint32_t PMC_PCSR;
#define SAM3_CKGR_UCKR            (SAM3_PMC_BASE + 0x001c)
	uint32_t CKGR_UCKR;
#define SAM3_CKGR_MOR             (SAM3_PMC_BASE + 0x0020)
	uint32_t CKGR_MOR;
#define SAM3_CKGR_MCFR            (SAM3_PMC_BASE + 0x0024)
	uint32_t CKGR_MCFR;
#define SAM3_CKGR_PLLAR           (SAM3_PMC_BASE + 0x0028)
	uint32_t CKGR_PLLAR;
#define SAM3_PMC_MCKR             (SAM3_PMC_BASE + 0x0030)
	uint32_t PMC_MCKR;
#define SAM3_PMC_PCK0             (SAM3_PMC_BASE + 0x0040)
	uint32_t PMC_PCK0;
#define SAM3_PMC_PCK1             (SAM3_PMC_BASE + 0x0044)
	uint32_t PMC_PCK1;
#define SAM3_PMC_PCK2             (SAM3_PMC_BASE + 0x0048)
	uint32_t PMC_PCK2;
#define SAM3_PMC_SR               (SAM3_PMC_BASE + 0x0068)
	uint32_t PMC_SR;
#define SAM3_PMC_IMR              (SAM3_PMC_BASE + 0x006c)
	uint32_t PMC_IMR;
#define SAM3_PMC_FSMR             (SAM3_PMC_BASE + 0x0070)
	uint32_t PMC_FSMR;
#define SAM3_PMC_FSPR             (SAM3_PMC_BASE + 0x0074)
	uint32_t PMC_FSPR;
};

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/*
 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
 * the flash wait state (FWS) should be set to 6. It seems like that the
 * cause of the problem is not the flash itself, but the flash write
 * buffer. Ie the wait states have to be set before writing into the
 * buffer.
 * Tested and confirmed with SAM3N and SAM3U
 */
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struct sam3_bank_private {
	int probed;
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	/* DANGER: THERE ARE DRAGONS HERE.. */
	/* NOTE: If you add more 'ghost' pointers */
	/* be aware that you must *manually* update */
	/* these pointers in the function sam3_GetDetails() */
	/* See the comment "Here there be dragons" */
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	/* so we can find the chip we belong to */
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	struct sam3_chip *pChip;
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	/* so we can find the original bank pointer */
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	struct flash_bank *pBank;
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	unsigned bank_number;
	uint32_t controller_address;
	uint32_t base_address;
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	uint32_t flash_wait_states;
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	bool present;
	unsigned size_bytes;
	unsigned nsectors;
	unsigned sector_size;
	unsigned page_size;
};

struct sam3_chip_details {
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	/* THERE ARE DRAGONS HERE.. */
	/* note: If you add pointers here */
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	/* be careful about them as they */
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	/* may need to be updated inside */
	/* the function: "sam3_GetDetails() */
	/* which copy/overwrites the */
	/* 'runtime' copy of this structure */
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	uint32_t chipid_cidr;
	const char *name;

	unsigned n_gpnvms;
#define SAM3_N_NVM_BITS 3
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	unsigned gpnvm[SAM3_N_NVM_BITS];
	unsigned total_flash_size;
	unsigned total_sram_size;
	unsigned n_banks;
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#define SAM3_MAX_FLASH_BANKS 2
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	/* these are "initialized" from the global const data */
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	struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
};

struct sam3_chip {
	struct sam3_chip *next;
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	int probed;
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	/* this is "initialized" from the global const structure */
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	struct sam3_chip_details details;
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	struct target *target;
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	struct sam3_cfg cfg;
};


struct sam3_reg_list {
	uint32_t address;  size_t struct_offset; const char *name;
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	void (*explain_func)(struct sam3_chip *pInfo);
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};

static struct sam3_chip *all_sam3_chips;

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static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
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{
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	struct target *t;
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	static struct sam3_chip *p;

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	t = get_current_target(cmd_ctx);
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	if (!t) {
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		command_print(cmd_ctx, "No current target?");
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		return NULL;
	}

	p = all_sam3_chips;
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	if (!p) {
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		/* this should not happen */
		/* the command is not registered until the chip is created? */
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		command_print(cmd_ctx, "No SAM3 chips exist?");
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		return NULL;
	}

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	while (p) {
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		if (p->target == t)
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			return p;
		p = p->next;
	}
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	command_print(cmd_ctx, "Cannot find SAM3 chip?");
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	return NULL;
}

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/* these are used to *initialize* the "pChip->details" structure. */
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static const struct sam3_chip_details all_sam3_details[] = {
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	/* Start at91sam3u* series */
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	{
		.chipid_cidr    = 0x28100960,
		.name           = "at91sam3u4e",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 52 * 1024,
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		.n_gpnvms       = 3,
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		.n_banks        = 2,

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		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */
		/* NOTE: banks 0 & 1 switch places */
		/*     if gpnvm[2] == 0 */
		/*         Bank0 is the boot rom */
		/*      else */
		/*         Bank1 is the boot rom */
		/*      endif */
/*		.bank[0] = { */
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		{
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			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_U,
				.controller_address = 0x400e0800,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 128 * 1024,
				.nsectors   = 16,
				.sector_size = 8192,
				.page_size   = 256,
			},

/*		.bank[1] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 1,
				.base_address = FLASH_BANK1_BASE_U,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 128 * 1024,
				.nsectors   = 16,
				.sector_size = 8192,
				.page_size   = 256,
			},
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		},
	},

	{
		.chipid_cidr    = 0x281a0760,
		.name           = "at91sam3u2e",
		.total_flash_size     = 128 * 1024,
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		.total_sram_size      = 36 * 1024,
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		.n_gpnvms       = 2,
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		.n_banks        = 1,

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		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
/*		.bank[0] = { */
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		{
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			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_U,
				.controller_address = 0x400e0800,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 128 * 1024,
				.nsectors   = 16,
				.sector_size = 8192,
				.page_size   = 256,
			},
/*		  .bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
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		},
	},
	{
		.chipid_cidr    = 0x28190560,
		.name           = "at91sam3u1e",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 20 * 1024,
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		.n_gpnvms       = 2,
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		.n_banks        = 1,

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		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */

/*		.bank[0] = { */
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		{
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			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_U,
				.controller_address = 0x400e0800,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 64 * 1024,
				.nsectors   = 8,
				.sector_size = 8192,
				.page_size   = 256,
			},

/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
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		},
	},
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	{
		.chipid_cidr    = 0x28000960,
		.name           = "at91sam3u4c",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 52 * 1024,
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		.n_gpnvms       = 3,
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		.n_banks        = 2,

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		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */
		/* NOTE: banks 0 & 1 switch places */
		/*     if gpnvm[2] == 0 */
		/*         Bank0 is the boot rom */
		/*      else */
		/*         Bank1 is the boot rom */
		/*      endif */
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		{
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			{
/*		.bank[0] = { */
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_U,
				.controller_address = 0x400e0800,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 128 * 1024,
				.nsectors   = 16,
				.sector_size = 8192,
				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 1,
				.base_address = FLASH_BANK1_BASE_U,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 128 * 1024,
				.nsectors   = 16,
				.sector_size = 8192,
				.page_size   = 256,
			},
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		},
	},

	{
		.chipid_cidr    = 0x280a0760,
		.name           = "at91sam3u2c",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 36 * 1024,
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		.n_gpnvms       = 2,
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		.n_banks        = 1,

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		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
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		{
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/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_U,
				.controller_address = 0x400e0800,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 128 * 1024,
				.nsectors   = 16,
				.sector_size = 8192,
				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
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		},
	},
	{
		.chipid_cidr    = 0x28090560,
		.name           = "at91sam3u1c",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 20 * 1024,
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		.n_gpnvms       = 2,
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		.n_banks        = 1,

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		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */
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		{
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/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_U,
				.controller_address = 0x400e0800,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 64 * 1024,
				.nsectors   = 8,
				.sector_size = 8192,
				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
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		},
	},

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	/* Start at91sam3s* series */
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	/* Note: The preliminary at91sam3s datasheet says on page 302 */
	/* that the flash controller is at address 0x400E0800. */
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	/* This is _not_ the case, the controller resides at address 0x400e0a00. */
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	{
		.chipid_cidr    = 0x28A00960,
		.name           = "at91sam3s4c",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 48 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
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/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 256 * 1024,
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				.nsectors   = 16,
				.sector_size = 16384,
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				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
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		},
	},

	{
		.chipid_cidr    = 0x28900960,
		.name           = "at91sam3s4b",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 48 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
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/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 256 * 1024,
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				.nsectors   = 16,
				.sector_size = 16384,
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				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
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		},
	},
	{
		.chipid_cidr    = 0x28800960,
		.name           = "at91sam3s4a",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 48 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
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/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 256 * 1024,
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				.nsectors   = 16,
				.sector_size = 16384,
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				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
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		},
	},
	{
		.chipid_cidr    = 0x28AA0760,
		.name           = "at91sam3s2c",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 32 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
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/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 128 * 1024,
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				.nsectors   = 8,
				.sector_size = 16384,
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				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
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		},
	},
	{
		.chipid_cidr    = 0x289A0760,
		.name           = "at91sam3s2b",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 32 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
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/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 128 * 1024,
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				.nsectors   = 8,
				.sector_size = 16384,
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				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
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		},
	},
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	{
		.chipid_cidr    = 0x298B0A60,
		.name           = "at91sam3sd8a",
		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 2,
		{
/*			.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_SD,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes =  256 * 1024,
				.nsectors   =  16,
				.sector_size = 32768,
				.page_size   = 256,
			  },
/*			.bank[1] = { */
			  {
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 1,
				.base_address = FLASH_BANK1_BASE_512K_SD,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes =  256 * 1024,
				.nsectors   =  16,
				.sector_size = 32768,
				.page_size   = 256,
			},
		},
	},
	{
		.chipid_cidr    = 0x299B0A60,
		.name           = "at91sam3sd8b",
		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 2,
		{
/*			.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_SD,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes =  256 * 1024,
				.nsectors   =  16,
				.sector_size = 32768,
				.page_size   = 256,
			  },
/*			.bank[1] = { */
			  {
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 1,
				.base_address = FLASH_BANK1_BASE_512K_SD,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes =  256 * 1024,
				.nsectors   =  16,
				.sector_size = 32768,
				.page_size   = 256,
			},
		},
	},
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	{
		.chipid_cidr    = 0x29ab0a60,
		.name           = "at91sam3sd8c",
		.total_flash_size     = 512 * 1024,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 2,
		{
/*			.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK0_BASE_SD,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes =  256 * 1024,
				.nsectors   =  16,
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				.sector_size = 32768,
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				.page_size   = 256,
			  },
/*			.bank[1] = { */
			  {
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 1,
				.base_address = FLASH_BANK1_BASE_512K_SD,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes =  256 * 1024,
				.nsectors   =  16,
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				.sector_size = 32768,
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				.page_size   = 256,
			},
		},
	},
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	{
		.chipid_cidr    = 0x288A0760,
		.name           = "at91sam3s2a",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 32 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
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/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 128 * 1024,
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				.nsectors   = 8,
				.sector_size = 16384,
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				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
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		},
	},
	{
		.chipid_cidr    = 0x28A90560,
		.name           = "at91sam3s1c",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 16 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
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/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 64 * 1024,
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				.nsectors   = 4,
				.sector_size = 16384,
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				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
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		},
	},
	{
		.chipid_cidr    = 0x28990560,
		.name           = "at91sam3s1b",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 16 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
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/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 64 * 1024,
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				.nsectors   = 4,
				.sector_size = 16384,
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				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
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		},
	},
	{
		.chipid_cidr    = 0x28890560,
		.name           = "at91sam3s1a",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 16 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
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/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 64 * 1024,
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				.nsectors   = 4,
				.sector_size = 16384,
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				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
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		},
	},
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	{
		.chipid_cidr    = 0x288B0A60,
		.name           = "at91sam3s8a",
		.total_flash_size     = 256 * 2048,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 256 * 2048,
				.nsectors   = 16,
				.sector_size = 32768,
				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
		},
	},
	{
		.chipid_cidr    = 0x289B0A60,
		.name           = "at91sam3s8b",
		.total_flash_size     = 256 * 2048,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 256 * 2048,
				.nsectors   = 16,
				.sector_size = 32768,
				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
		},
	},
	{
		.chipid_cidr    = 0x28AB0A60,
		.name           = "at91sam3s8c",
		.total_flash_size     = 256 * 2048,
		.total_sram_size      = 64 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
/*		.bank[0] = { */
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_S,
				.controller_address = 0x400e0a00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 256 * 2048,
				.nsectors   = 16,
				.sector_size = 32768,
				.page_size   = 256,
			},
/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,

			},
		},
	},
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	/* Start at91sam3n* series */
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	{
		.chipid_cidr    = 0x29540960,
		.name           = "at91sam3n4c",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 24 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 1,

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		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */
		/* NOTE: banks 0 & 1 switch places */
		/*     if gpnvm[2] == 0 */
		/*         Bank0 is the boot rom */
		/*      else */
		/*         Bank1 is the boot rom */
		/*      endif */
/*		.bank[0] = { */
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		{
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			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_N,
				.controller_address = 0x400e0A00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 256 * 1024,
				.nsectors   = 16,
				.sector_size = 16384,
				.page_size   = 256,
			},

/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
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		},
	},

	{
		.chipid_cidr    = 0x29440960,
		.name           = "at91sam3n4b",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 24 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 1,

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		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */
		/* NOTE: banks 0 & 1 switch places */
		/*     if gpnvm[2] == 0 */
		/*         Bank0 is the boot rom */
		/*      else */
		/*         Bank1 is the boot rom */
		/*      endif */
/*		.bank[0] = { */
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		{
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			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_N,
				.controller_address = 0x400e0A00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 256 * 1024,
				.nsectors   = 16,
				.sector_size = 16384,
				.page_size   = 256,
			},

/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
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		},
	},

	{
		.chipid_cidr    = 0x29340960,
		.name           = "at91sam3n4a",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 24 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 1,

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		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */
		/* NOTE: banks 0 & 1 switch places */
		/*     if gpnvm[2] == 0 */
		/*         Bank0 is the boot rom */
		/*      else */
		/*         Bank1 is the boot rom */
		/*      endif */
/*		.bank[0] = { */
1200
		{
1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_N,
				.controller_address = 0x400e0A00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 256 * 1024,
				.nsectors   = 16,
				.sector_size = 16384,
				.page_size   = 256,
			},

/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232
		},
	},

	{
		.chipid_cidr    = 0x29590760,
		.name           = "at91sam3n2c",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 16 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 1,

1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248
		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */
		/* NOTE: banks 0 & 1 switch places */
		/*     if gpnvm[2] == 0 */
		/*         Bank0 is the boot rom */
		/*      else */
		/*         Bank1 is the boot rom */
		/*      endif */
/*		.bank[0] = { */
1249
		{
1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_N,
				.controller_address = 0x400e0A00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 128 * 1024,
				.nsectors   = 8,
				.sector_size = 16384,
				.page_size   = 256,
			},

/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281
		},
	},

	{
		.chipid_cidr    = 0x29490760,
		.name           = "at91sam3n2b",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 16 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 1,

1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297
		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */
		/* NOTE: banks 0 & 1 switch places */
		/*     if gpnvm[2] == 0 */
		/*         Bank0 is the boot rom */
		/*      else */
		/*         Bank1 is the boot rom */
		/*      endif */
/*		.bank[0] = { */
1298
		{
1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_N,
				.controller_address = 0x400e0A00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 128 * 1024,
				.nsectors   = 8,
				.sector_size = 16384,
				.page_size   = 256,
			},

/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330
		},
	},

	{
		.chipid_cidr    = 0x29390760,
		.name           = "at91sam3n2a",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 16 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 1,

1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346
		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */
		/* NOTE: banks 0 & 1 switch places */
		/*     if gpnvm[2] == 0 */
		/*         Bank0 is the boot rom */
		/*      else */
		/*         Bank1 is the boot rom */
		/*      endif */
/*		.bank[0] = { */
1347
		{
1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_N,
				.controller_address = 0x400e0A00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 128 * 1024,
				.nsectors   = 8,
				.sector_size = 16384,
				.page_size   = 256,
			},

/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379
		},
	},

	{
		.chipid_cidr    = 0x29580560,
		.name           = "at91sam3n1c",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 8 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 1,

1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395
		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */
		/* NOTE: banks 0 & 1 switch places */
		/*     if gpnvm[2] == 0 */
		/*         Bank0 is the boot rom */
		/*      else */
		/*         Bank1 is the boot rom */
		/*      endif */
/*		.bank[0] = { */
1396
		{
1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_N,
				.controller_address = 0x400e0A00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 64 * 1024,
				.nsectors   = 4,
				.sector_size = 16384,
				.page_size   = 256,
			},

/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428
		},
	},

	{
		.chipid_cidr    = 0x29480560,
		.name           = "at91sam3n1b",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 8 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 1,

1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444
		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */
		/* NOTE: banks 0 & 1 switch places */
		/*     if gpnvm[2] == 0 */
		/*         Bank0 is the boot rom */
		/*      else */
		/*         Bank1 is the boot rom */
		/*      endif */
/*		.bank[0] = { */
1445
		{
1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_N,
				.controller_address = 0x400e0A00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 64 * 1024,
				.nsectors   = 4,
				.sector_size = 16384,
				.page_size   = 256,
			},

/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477
		},
	},

	{
		.chipid_cidr    = 0x29380560,
		.name           = "at91sam3n1a",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 8 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 1,

1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493
		/* System boots at address 0x0 */
		/* gpnvm[1] = selects boot code */
		/*     if gpnvm[1] == 0 */
		/*         boot is via "SAMBA" (rom) */
		/*     else */
		/*         boot is via FLASH */
		/*         Selection is via gpnvm[2] */
		/*     endif */
		/*  */
		/* NOTE: banks 0 & 1 switch places */
		/*     if gpnvm[2] == 0 */
		/*         Bank0 is the boot rom */
		/*      else */
		/*         Bank1 is the boot rom */
		/*      endif */
/*		.bank[0] = { */
1494
		{
1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515
			{
				.probed = 0,
				.pChip  = NULL,
				.pBank  = NULL,
				.bank_number = 0,
				.base_address = FLASH_BANK_BASE_N,
				.controller_address = 0x400e0A00,
				.flash_wait_states = 6,	/* workaround silicon bug */
				.present = 1,
				.size_bytes = 64 * 1024,
				.nsectors   = 4,
				.sector_size = 16384,
				.page_size   = 256,
			},

/*		.bank[1] = { */
			{
				.present = 0,
				.probed = 0,
				.bank_number = 1,
			},
1516 1517 1518
		},
	},