arm7_9_common.c 76.6 KB
Newer Older
1
2
3
4
/***************************************************************************
 *   Copyright (C) 2005 by Dominic Rath                                    *
 *   Dominic.Rath@gmx.de                                                   *
 *                                                                         *
5
 *   Copyright (C) 2007,2008 yvind Harboe                                 *
6
7
 *   oyvind.harboe@zylin.com                                               *
 *                                                                         *
8
9
10
 *   Copyright (C) 2008 by Spencer Oliver                                  *
 *   spen@spen-soft.co.uk                                                  *
 *                                                                         *
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 ***************************************************************************/
26
#ifdef HAVE_CONFIG_H
27
#include "config.h"
28
29
30
#endif

#include "replacements.h"
31
32
33

#include "embeddedice.h"
#include "target.h"
34
#include "target_request.h"
35
36
37
38
39
40
#include "armv4_5.h"
#include "arm_jtag.h"
#include "jtag.h"
#include "log.h"
#include "arm7_9_common.h"
#include "breakpoints.h"
oharboe's avatar
oharboe committed
41
#include "time_support.h"
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

#include <stdlib.h>
#include <string.h>
#include <unistd.h>

#include <sys/types.h>
#include <sys/stat.h>
#include <sys/time.h>
#include <errno.h>

int arm7_9_debug_entry(target_t *target);
int arm7_9_enable_sw_bkpts(struct target_s *target);

/* command handler forward declarations */
int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
61
int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
62
int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
63
int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
64

65

66
67
68
69
70
static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
{
	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
	arm7_9->sw_breakpoints_added = 0;
71
	arm7_9->wp0_used = 0;
72
73
	arm7_9->wp1_used = arm7_9->wp1_used_default;
	arm7_9->wp_available = arm7_9->wp_available_max;
74

75
76
77
78
79
80
81
	return jtag_execute_queue();
}

/* set up embedded ice registers */
static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
{
	if (arm7_9->sw_breakpoints_added)
82
	{
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
		return ERROR_OK;
	}
	if (arm7_9->wp_available < 1)
	{
		LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}
	arm7_9->wp_available--;
	
	/* pick a breakpoint unit */
	if (!arm7_9->wp0_used)
	{
		arm7_9->sw_breakpoints_added=1;
		arm7_9->wp0_used = 3;
	} else if (!arm7_9->wp1_used)
	{
		arm7_9->sw_breakpoints_added=2;
		arm7_9->wp1_used = 3;
	}
	else
	{
		LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
		return ERROR_FAIL;
106
	}
107

108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
	if (arm7_9->sw_breakpoints_added==1)
	{
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
	}
	else if (arm7_9->sw_breakpoints_added==2)
	{
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
	}
	else
125
	{
126
127
		LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
		return ERROR_FAIL;
128
	}
129

130
	return jtag_execute_queue();
131
132
}

133
134
/* set things up after a reset / on startup */
int arm7_9_setup(target_t *target)
135
{
136
137
138
139
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;

	return arm7_9_clear_watchpoints(arm7_9);
140
141
}

142

143
144
145
146
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
147

148
149
150
151
	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
	{
		return -1;
	}
152

153
154
155
156
	if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
	{
		return -1;
	}
157

158
159
	*armv4_5_p = armv4_5;
	*arm7_9_p = arm7_9;
160

161
162
163
	return ERROR_OK;
}

164
165
166
/* we set up the breakpoint even if it is already set. Some action, e.g. reset
 * might have erased the values in embedded ice
 */
167
168
169
170
int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
171
	int retval=ERROR_OK;
172

173
174
	if (target->state != TARGET_HALTED)
	{
175
		LOG_WARNING("target not halted");
176
177
		return ERROR_TARGET_NOT_HALTED;
	}
178

179
180
181
182
	if (breakpoint->type == BKPT_HARD)
	{
		/* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
		u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
183
		if (breakpoint->set==1)
184
185
186
187
188
189
190
		{
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
		}
191
		else if (breakpoint->set==2)
192
193
194
195
196
197
198
199
200
		{
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
		}
		else
		{
201
			LOG_ERROR("BUG: no hardware comparator available");
202
203
			return ERROR_OK;
		}
204
205

		retval=jtag_execute_queue();
206
207
208
	}
	else if (breakpoint->type == BKPT_SOFT)
	{
209
210
211
212
213
214
215
		if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK)
			return retval;
		
		/* did we already set this breakpoint? */
		if (breakpoint->set)
			return ERROR_OK;
		
216
217
		if (breakpoint->length == 4)
		{
ntfreak's avatar
ntfreak committed
218
			u32 verify = 0xffffffff;
219
			/* keep the original instruction in target endianness */
220
			target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
drath's avatar
drath committed
221
			/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
222
			target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
223

ntfreak's avatar
ntfreak committed
224
225
226
			target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
			if (verify != arm7_9->arm_bkpt)
			{
227
				LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
ntfreak's avatar
ntfreak committed
228
229
				return ERROR_OK;
			}
230
231
232
		}
		else
		{
ntfreak's avatar
ntfreak committed
233
			u16 verify = 0xffff;
234
			/* keep the original instruction in target endianness */
235
			target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
drath's avatar
drath committed
236
237
			/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
			target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
238

ntfreak's avatar
ntfreak committed
239
240
241
			target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
			if (verify != arm7_9->thumb_bkpt)
			{
242
				LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
ntfreak's avatar
ntfreak committed
243
244
				return ERROR_OK;
			}
245
246
247
248
		}
		breakpoint->set = 1;
	}

249
	return retval;
250
251
252
253
254
255
256

}

int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
257

258
259
	if (!breakpoint->set)
	{
260
		LOG_WARNING("breakpoint not set");
261
262
		return ERROR_OK;
	}
263

264
265
266
267
268
269
270
271
272
273
274
275
	if (breakpoint->type == BKPT_HARD)
	{
		if (breakpoint->set == 1)
		{
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
			arm7_9->wp0_used = 0;
		}
		else if (breakpoint->set == 2)
		{
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
			arm7_9->wp1_used = 0;
		}
276
		jtag_execute_queue();
277
278
279
280
		breakpoint->set = 0;
	}
	else
	{
281
		/* restore original instruction (kept in target endianness) */
282
283
		if (breakpoint->length == 4)
		{
284
285
286
287
288
			u32 current_instr;
			/* check that user program as not modified breakpoint instruction */
			target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
			if (current_instr==arm7_9->arm_bkpt)
				target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
289
290
291
		}
		else
		{
292
293
294
295
296
			u16 current_instr;
			/* check that user program as not modified breakpoint instruction */
			target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
			if (current_instr==arm7_9->thumb_bkpt)
				target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
297
298
299
300
301
302
303
		}
		breakpoint->set = 0;
	}

	return ERROR_OK;
}

304
int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
305
306
307
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
308

309
310
	if (target->state != TARGET_HALTED)
	{
311
		LOG_WARNING("target not halted");
312
313
		return ERROR_TARGET_NOT_HALTED;
	}
314
315
	
	if (arm7_9->breakpoint_count==0)
316
	{
317
318
319
320
		/* make sure we don't have any dangling breakpoints. This is vital upon 
		 * GDB connect/disconnect 
		 */
		arm7_9_clear_watchpoints(arm7_9);	
321
	}
322

323
	if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
324
	{
325
		LOG_INFO("no watchpoint unit available for hardware breakpoint");
326
327
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}
328

329
	if ((breakpoint->length != 2) && (breakpoint->length != 4))
330
	{
331
		LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
332
333
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}
334

335
	if (breakpoint->type == BKPT_HARD)
336
	{
337
		arm7_9->wp_available--;
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
		
		if (!arm7_9->wp0_used)
		{
			arm7_9->wp0_used = 1;
			breakpoint->set = 1;
		}
		else if (!arm7_9->wp1_used)
		{
			arm7_9->wp1_used = 1;
			breakpoint->set = 2;
		}
		else
		{
			LOG_ERROR("BUG: no hardware comparator available");
		}
	}
	
355

356
357
358
	arm7_9->breakpoint_count++;
	
	return arm7_9_set_breakpoint(target, breakpoint);
359
360
361
362
363
364
}

int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
365

366
	arm7_9_unset_breakpoint(target, breakpoint);
367

368
369
	if (breakpoint->type == BKPT_HARD)
		arm7_9->wp_available++;
370
371
372
373
374
375
376
	
	arm7_9->breakpoint_count--;
	if (arm7_9->breakpoint_count==0)
	{
		/* make sure we don't have any dangling breakpoints */
		arm7_9_clear_watchpoints(arm7_9);	
	}
377

378
379
380
381
382
383
384
385
386
	return ERROR_OK;
}

int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	int rw_mask = 1;
	u32 mask;
387

388
	mask = watchpoint->length - 1;
389

390
391
	if (target->state != TARGET_HALTED)
	{
392
		LOG_WARNING("target not halted");
393
394
		return ERROR_TARGET_NOT_HALTED;
	}
395

396
397
398
399
	if (watchpoint->rw == WPT_ACCESS)
		rw_mask = 0;
	else
		rw_mask = 1;
400

401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
	if (!arm7_9->wp0_used)
	{
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
		if( watchpoint->mask != 0xffffffffu )
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));

		jtag_execute_queue();
		watchpoint->set = 1;
		arm7_9->wp0_used = 2;
	}
	else if (!arm7_9->wp1_used)
	{
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
		if( watchpoint->mask != 0xffffffffu )
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));

		jtag_execute_queue();
		watchpoint->set = 2;
		arm7_9->wp1_used = 2;
428
	}
429
430
	else
	{
431
		LOG_ERROR("BUG: no hardware comparator available");
432
433
		return ERROR_OK;
	}
434

435
436
437
438
439
440
441
	return ERROR_OK;
}

int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
442

443
444
	if (target->state != TARGET_HALTED)
	{
445
		LOG_WARNING("target not halted");
446
447
		return ERROR_TARGET_NOT_HALTED;
	}
448

449
450
	if (!watchpoint->set)
	{
451
		LOG_WARNING("breakpoint not set");
452
453
		return ERROR_OK;
	}
454

455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
	if (watchpoint->set == 1)
	{
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
		jtag_execute_queue();
		arm7_9->wp0_used = 0;
	}
	else if (watchpoint->set == 2)
	{
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
		jtag_execute_queue();
		arm7_9->wp1_used = 0;
	}
	watchpoint->set = 0;

	return ERROR_OK;
}

472
int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
473
474
475
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
476

477
478
	if (target->state != TARGET_HALTED)
	{
479
		LOG_WARNING("target not halted");
480
481
		return ERROR_TARGET_NOT_HALTED;
	}
482

483
484
485
486
	if (arm7_9->wp_available < 1)
	{
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}
487

488
	if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
489
490
491
	{
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}
492

493
	arm7_9->wp_available--;
494

495
496
497
498
499
500
501
	return ERROR_OK;
}

int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
502

503
504
505
506
	if (watchpoint->set)
	{
		arm7_9_unset_watchpoint(target, watchpoint);
	}
507

508
	arm7_9->wp_available++;
509

510
511
512
	return ERROR_OK;
}

513
514


515
516
517
518

int arm7_9_execute_sys_speed(struct target_s *target)
{
	int retval;
519

520
521
522
523
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
524

525
526
	/* set RESTART instruction */
	jtag_add_end_state(TAP_RTI);
oharboe's avatar
oharboe committed
527
528
529
530
	if (arm7_9->need_bypass_before_restart) {
		arm7_9->need_bypass_before_restart = 0;
		arm_jtag_set_instr(jtag_info, 0xf, NULL);
	}
531
	arm_jtag_set_instr(jtag_info, 0x4, NULL);
532

oharboe's avatar
oharboe committed
533
534
535
	long long then=timeval_ms();
	int timeout;
	while (!(timeout=((timeval_ms()-then)>1000)))
536
537
538
539
540
541
542
543
	{
		/* read debug status register */
		embeddedice_read_reg(dbg_stat);
		if ((retval = jtag_execute_queue()) != ERROR_OK)
			return retval;
		if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
				   && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
			break;
oharboe's avatar
oharboe committed
544
545
546
547
548
549
550
		if (debug_level>=3)
		{
			alive_sleep(100);
		} else
		{
			keep_alive();
		}
551
	}
oharboe's avatar
oharboe committed
552
	if (timeout)
553
	{
554
		LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
555
556
		return ERROR_TARGET_TIMEOUT;
	}
557

558
559
560
561
562
	return ERROR_OK;
}

int arm7_9_execute_fast_sys_speed(struct target_s *target)
{
mifi's avatar
mifi committed
563
564
	static int set=0;
	static u8 check_value[4], check_mask[4];
565

566
567
568
569
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
570

571
572
	/* set RESTART instruction */
	jtag_add_end_state(TAP_RTI);
oharboe's avatar
oharboe committed
573
574
575
576
	if (arm7_9->need_bypass_before_restart) {
		arm7_9->need_bypass_before_restart = 0;
		arm_jtag_set_instr(jtag_info, 0xf, NULL);
	}
577
	arm_jtag_set_instr(jtag_info, 0x4, NULL);
578

mifi's avatar
mifi committed
579
580
581
	if (!set)
	{
		/* check for DBGACK and SYSCOMP set (others don't care) */
582

mifi's avatar
mifi committed
583
584
585
586
587
588
589
590
		/* NB! These are constants that must be available until after next jtag_execute() and
		   we evaluate the values upon first execution in lieu of setting up these constants
		   during early setup.
		*/
		buf_set_u32(check_value, 0, 32, 0x9);
		buf_set_u32(check_mask, 0, 32, 0x9);
		set=1;
	}
591

592
593
594
595
596
597
	/* read debug status register */
	embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);

	return ERROR_OK;
}

598
599
600
601
602
603
604
int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
	u32 *data;
	int i;
605

606
	data = malloc(size * (sizeof(u32)));
607

608
	embeddedice_receive(jtag_info, data, size);
609

610
611
612
613
	for (i = 0; i < size; i++)
	{
		h_u32_to_le(buffer + (i * 4), data[i]);
	}
614

615
	free(data);
616

617
618
619
620
621
622
	return ERROR_OK;
}

int arm7_9_handle_target_request(void *priv)
{
	target_t *target = priv;
623
624
	if (!target->type->examined)
		return ERROR_OK;
625
626
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
627
	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
628
	reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
629
630


631
632
	if (!target->dbg_msg_enabled)
		return ERROR_OK;
633

634
635
636
637
638
	if (target->state == TARGET_RUNNING)
	{
		/* read DCC control register */
		embeddedice_read_reg(dcc_control);
		jtag_execute_queue();
639

640
641
642
643
		/* check W bit */
		if (buf_get_u32(dcc_control->value, 1, 1) == 1)
		{
			u32 request;
644

645
646
647
648
			embeddedice_receive(jtag_info, &request, 1);
			target_request(target, request);
		}
	}
649

650
651
652
	return ERROR_OK;
}

653
int arm7_9_poll(target_t *target)
654
655
656
657
658
659
660
661
662
663
{
	int retval;
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];

	/* read debug status register */
	embeddedice_read_reg(dbg_stat);
	if ((retval = jtag_execute_queue()) != ERROR_OK)
	{
664
		return retval;
665
	}
666

667
668
	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
	{
669
/*		LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
670
		if (target->state == TARGET_UNKNOWN)
671
		{
672
			target->state = TARGET_RUNNING;
673
			LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
674
675
676
		}
		if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
		{
677
678
679
			int check_pc=0;
			if (target->state == TARGET_RESET)
			{
oharboe's avatar
   
oharboe committed
680
				if (target->reset_halt)
681
682
683
684
685
686
687
				{
					if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
					{
						check_pc = 1;
					}
				}
			}
688

689
			target->state = TARGET_HALTED;
690

691
692
			if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
				return retval;
693

694
695
696
697
698
699
			if (check_pc)
			{
				reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
				u32 t=*((u32 *)reg->value);
				if (t!=0)
				{
700
					LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
701
702
				}
			}
703

704
705
706
707
708
709
710
			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
		}
		if (target->state == TARGET_DEBUG_RUNNING)
		{
			target->state = TARGET_HALTED;
			if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
				return retval;
711

712
713
			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
		}
714
715
		if (target->state != TARGET_HALTED)
		{
716
			LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
717
		}
718
	}
719
720
721
722
723
	else
	{
		if (target->state != TARGET_DEBUG_RUNNING)
			target->state = TARGET_RUNNING;
	}
724

725
	return ERROR_OK;
726
727
}

728
729
730
/*
  Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
  in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
oharboe's avatar
   
oharboe committed
731
  while the core is held in reset(SRST). It isn't possible to program the halt
732
733
734
735
  condition once reset was asserted, hence a hook that allows the target to set
  up its reset-halt condition prior to asserting reset.
*/

736
737
int arm7_9_assert_reset(target_t *target)
{
738
739
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
740
741
	LOG_DEBUG("target->state: %s", 
		  Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
742

743
744
745
746
747
	if (!(jtag_reset_config & RESET_HAS_SRST))
	{
		LOG_ERROR("Can't assert SRST");
		return ERROR_FAIL;
	}
oharboe's avatar
   
oharboe committed
748

oharboe's avatar
   
oharboe committed
749
	if (target->reset_halt)
750
	{
oharboe's avatar
   
oharboe committed
751
752
753
		/*
		 * Some targets do not support communication while SRST is asserted. We need to
		 * set up the reset vector catch here.
754
		 *
oharboe's avatar
   
oharboe committed
755
		 * If TRST is asserted, then these settings will be reset anyway, so setting them
756
		 * here is harmless.
oharboe's avatar
   
oharboe committed
757
758
759
760
761
762
763
764
765
		 */
		if (arm7_9->has_vector_catch)
		{
			/* program vector catch register to catch reset vector */
			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
		}
		else
		{
			/* program watchpoint unit to match on reset vector address */
766
			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
oharboe's avatar
   
oharboe committed
767
			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
768
769
770
			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
oharboe's avatar
   
oharboe committed
771
		}
772
773
	}

oharboe's avatar
   
oharboe committed
774
	/* here we should issue a srst only, but we may have to assert trst as well */
775
	if (jtag_reset_config & RESET_SRST_PULLS_TRST)
776
	{
777
778
779
780
		jtag_add_reset(1, 1);
	} else
	{
		jtag_add_reset(0, 1);
781
	}
782

oharboe's avatar
   
oharboe committed
783

784
785
	target->state = TARGET_RESET;
	jtag_add_sleep(50000);
oharboe's avatar
   
oharboe committed
786

787
788
	armv4_5_invalidate_core_regs(target);

789
790
791
792
793
794
    if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
	{
		/* debug entry was already prepared in arm7_9_assert_reset() */
		target->debug_reason = DBG_REASON_DBGRQ;
	}
	
795
796
797
798
799
800
	return ERROR_OK;

}

int arm7_9_deassert_reset(target_t *target)
{
801
	int retval=ERROR_OK;
802
803
804
	LOG_DEBUG("target->state: %s", 
		  Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);

805

806
807
	/* deassert reset lines */
	jtag_add_reset(0, 0);
808

809
	if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
810
	{
811
		LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
812
813
814
		/* set up embedded ice registers again */
		if ((retval=target->type->examine(target))!=ERROR_OK)
			return retval;
815
816
817
818
819
820
821
822
823
824
825

		if ((retval=target_poll(target))!=ERROR_OK)
		{
			return retval;
		}
		
		if ((retval=target_halt(target))!=ERROR_OK)
		{
			return retval;
		}
		
826
827
	}
	return retval;
828
829
}

830
831
832
833
834
int arm7_9_clear_halt(target_t *target)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
835

836
837
	/* we used DBGRQ only if we didn't come out of reset */
	if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
838
839
840
	{
		/* program EmbeddedICE Debug Control Register to deassert DBGRQ
		 */
841
		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
842
843
844
845
		embeddedice_store_reg(dbg_ctrl);
	}
	else
	{
846
		if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
847
		{
848
849
850
851
852
853
854
855
856
857
858
859
			/* if we came out of reset, and vector catch is supported, we used
			 * vector catch to enter debug state
			 * restore the register in that case
			 */
			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
		}
		else
		{
			/* restore registers if watchpoint unit 0 was in use
			 */
			if (arm7_9->wp0_used)
			{
860
861
862
863
				if (arm7_9->debug_entry_from_reset)
				{
					embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
				}
864
865
866
867
				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
			}
868
			/* control value always has to be restored, as it was either disabled,
869
870
871
			 * or enabled with possibly different bits
			 */
			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
872
873
		}
	}
874

875
876
877
	return ERROR_OK;
}

878
879
880
881
882
int arm7_9_soft_reset_halt(struct target_s *target)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
883
	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
884
	int i;
oharboe's avatar
   
oharboe committed
885
	int retval;
886

887
	if ((retval=target_halt(target))!=ERROR_OK)
oharboe's avatar
   
oharboe committed
888
		return retval;
889

oharboe's avatar
oharboe committed
890
891
892
	long long then=timeval_ms();
	int timeout;
	while (!(timeout=((timeval_ms()-then)>1000)))
893
	{
oharboe's avatar
   
oharboe committed
894
895
		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
			break;
896
		embeddedice_read_reg(dbg_stat);
oharboe's avatar
   
oharboe committed
897
898
		if ((retval=jtag_execute_queue())!=ERROR_OK)
			return retval;
oharboe's avatar
oharboe committed
899
900
901
902
903
904
905
		if (debug_level>=3)
		{
			alive_sleep(100);
		} else
		{
			keep_alive();
		}
oharboe's avatar
   
oharboe committed
906
	}
oharboe's avatar
oharboe committed
907
	if (timeout)
oharboe's avatar
   
oharboe committed
908
	{
909
		LOG_ERROR("Failed to halt CPU after 1 sec");
oharboe's avatar
   
oharboe committed
910
		return ERROR_TARGET_TIMEOUT;
911
912
	}
	target->state = TARGET_HALTED;
913

914
915
916
917
918
919
920
	/* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
	 * ensure that DBGRQ is cleared
	 */
	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
	embeddedice_store_reg(dbg_ctrl);
921

922
	arm7_9_clear_halt(target);
923

924
925
926
927
	/* if the target is in Thumb state, change to ARM state */
	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
	{
		u32 r0_thumb, pc_thumb;
928
		LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
929
930
931
932
		/* Entered debug from Thumb mode */
		armv4_5->core_state = ARMV4_5_STATE_THUMB;
		arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
	}
933

934
935
	/* all register content is now invalid */
	armv4_5_invalidate_core_regs(target);
936

937
938
939
940
	/* SVC, ARM state, IRQ and FIQ disabled */
	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
941

942
943
944
945
	/* start fetching from 0x0 */
	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
	armv4_5->core_cache->reg_list[15].dirty = 1;
	armv4_5->core_cache->reg_list[15].valid = 1;
946

947
948
	armv4_5->core_mode = ARMV4_5_MODE_SVC;
	armv4_5->core_state = ARMV4_5_STATE_ARM;
949
950
951

	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
		return ERROR_FAIL;
952

953
954
	/* reset registers */
	for (i = 0; i <= 14; i++)
955
	{
956
957
958
959
		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
	}
960

961
	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
962

963
964
965
966
967
	return ERROR_OK;
}

int arm7_9_halt(target_t *target)
{
968
	if (target->state==TARGET_RESET)
969
	{
970
		LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
971
972
973
		return ERROR_OK;
	}

974
975
976
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
977

978
979
	LOG_DEBUG("target->state: %s", 
		  Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
980

981
982
	if (target->state == TARGET_HALTED)
	{
983
		LOG_DEBUG("target was already halted");
oharboe's avatar
   
oharboe committed
984
		return ERROR_OK;
985
	}
986

987
988
	if (target->state == TARGET_UNKNOWN)
	{
989
		LOG_WARNING("target was in unknown state when halt was requested");
990
	}
991

992
993
994
995
	if (arm7_9->use_dbgrq)
	{
		/* program EmbeddedICE Debug Control Register to assert DBGRQ
		 */
oharboe's avatar
oharboe committed
996
997
998
		if (arm7_9->set_special_dbgrq) {
			arm7_9->set_special_dbgrq(target);
		} else {
999
			buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
oharboe's avatar
oharboe committed
1000
			embeddedice_store_reg(dbg_ctrl);
For faster browsing, not all history is shown. View entire blame