mips_m4k.c 27.6 KB
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/***************************************************************************
 *   Copyright (C) 2008 by Spencer Oliver                                  *
 *   spen@spen-soft.co.uk                                                  *
 *                                                                         *
 *   Copyright (C) 2008 by David T.L. Wong                                 *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 ***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "mips32.h"
#include "mips_m4k.h"
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#include "mips32_dmaacc.h"
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#include "target_type.h"
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/* cli handling */

/* forward declarations */
int mips_m4k_poll(target_t *target);
int mips_m4k_halt(struct target_s *target);
int mips_m4k_soft_reset_halt(struct target_s *target);
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int mips_m4k_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
int mips_m4k_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
int mips_m4k_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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int mips_m4k_quit(void);
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int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp);
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int mips_m4k_examine(struct target_s *target);
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int mips_m4k_assert_reset(target_t *target);
int mips_m4k_deassert_reset(target_t *target);
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int mips_m4k_checksum_memory(target_t *target, uint32_t address, uint32_t size, uint32_t *checksum);
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target_type_t mips_m4k_target =
{
	.name = "mips_m4k",

	.poll = mips_m4k_poll,
	.arch_state = mips32_arch_state,

	.target_request_data = NULL,

	.halt = mips_m4k_halt,
	.resume = mips_m4k_resume,
	.step = mips_m4k_step,

	.assert_reset = mips_m4k_assert_reset,
	.deassert_reset = mips_m4k_deassert_reset,
	.soft_reset_halt = mips_m4k_soft_reset_halt,
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	.get_gdb_reg_list = mips32_get_gdb_reg_list,

	.read_memory = mips_m4k_read_memory,
	.write_memory = mips_m4k_write_memory,
	.bulk_write_memory = mips_m4k_bulk_write_memory,
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	.checksum_memory = mips_m4k_checksum_memory,
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	.blank_check_memory = NULL,
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	.run_algorithm = mips32_run_algorithm,

	.add_breakpoint = mips_m4k_add_breakpoint,
	.remove_breakpoint = mips_m4k_remove_breakpoint,
	.add_watchpoint = mips_m4k_add_watchpoint,
	.remove_watchpoint = mips_m4k_remove_watchpoint,

	.register_commands = mips_m4k_register_commands,
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	.target_create = mips_m4k_target_create,
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	.init_target = mips_m4k_init_target,
	.examine = mips_m4k_examine,
	.quit = mips_m4k_quit
};

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int mips_m4k_examine_debug_reason(target_t *target)
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{
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	uint32_t break_status;
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	int retval;
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	if ((target->debug_reason != DBG_REASON_DBGRQ)
		&& (target->debug_reason != DBG_REASON_SINGLESTEP))
	{
		/* get info about inst breakpoint support */
		if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
			return retval;
		if (break_status & 0x1f)
		{
			/* we have halted on a  breakpoint */
			if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
				return retval;
			target->debug_reason = DBG_REASON_BREAKPOINT;
		}
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		/* get info about data breakpoint support */
		if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
			return retval;
		if (break_status & 0x1f)
		{
			/* we have halted on a  breakpoint */
			if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
				return retval;
			target->debug_reason = DBG_REASON_WATCHPOINT;
		}
	}
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	return ERROR_OK;
}

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int mips_m4k_debug_entry(target_t *target)
{
	mips32_common_t *mips32 = target->arch_info;
	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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	uint32_t debug_reg;
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	/* read debug register */
	mips_ejtag_read_debug(ejtag_info, &debug_reg);
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	/* make sure break uit configured */
	mips32_configure_break_unit(target);
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	/* attempt to find halt reason */
	mips_m4k_examine_debug_reason(target);
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	/* clear single step if active */
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	if (debug_reg & EJTAG_DEBUG_DSS)
	{
		/* stopped due to single step - clear step bit */
		mips_ejtag_config_step(ejtag_info, 0);
	}
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	mips32_save_context(target);
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	LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
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		*(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value),
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		  target_state_name(target));
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	return ERROR_OK;
}

int mips_m4k_poll(target_t *target)
{
	int retval;
	mips32_common_t *mips32 = target->arch_info;
	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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	uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
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	/* read ejtag control reg */
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	jtag_set_end_state(TAP_IDLE);
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	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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	/* clear this bit before handling polling
	 * as after reset registers will read zero */
	if (ejtag_ctrl & EJTAG_CTRL_ROCC)
	{
		/* we have detected a reset, clear flag
		 * otherwise ejtag will not work */
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		jtag_set_end_state(TAP_IDLE);
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		ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
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		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
		LOG_DEBUG("Reset Detected");
	}
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	/* check for processor halted */
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	if (ejtag_ctrl & EJTAG_CTRL_BRKST)
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	{
		if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
		{
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			jtag_set_end_state(TAP_IDLE);
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			mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
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			target->state = TARGET_HALTED;
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			if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
				return retval;
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			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
		}
		else if (target->state == TARGET_DEBUG_RUNNING)
		{
			target->state = TARGET_HALTED;
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			if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
				return retval;
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			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
		}
	}
	else
	{
		target->state = TARGET_RUNNING;
	}
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//	LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
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	return ERROR_OK;
}

int mips_m4k_halt(struct target_s *target)
{
	mips32_common_t *mips32 = target->arch_info;
	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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	LOG_DEBUG("target->state: %s",
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		  target_state_name(target));
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	if (target->state == TARGET_HALTED)
	{
		LOG_DEBUG("target was already halted");
		return ERROR_OK;
	}
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	if (target->state == TARGET_UNKNOWN)
	{
		LOG_WARNING("target was in unknown state when halt was requested");
	}
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	if (target->state == TARGET_RESET)
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	{
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		if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
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		{
			LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
			return ERROR_TARGET_FAILURE;
		}
		else
		{
			/* we came here in a reset_halt or reset_init sequence
			 * debug entry was already prepared in mips32_prepare_reset_halt()
			 */
			target->debug_reason = DBG_REASON_DBGRQ;
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			return ERROR_OK;
		}
	}
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	/* break processor */
	mips_ejtag_enter_debug(ejtag_info);
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	target->debug_reason = DBG_REASON_DBGRQ;
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	return ERROR_OK;
}

int mips_m4k_assert_reset(target_t *target)
{
	mips32_common_t *mips32 = target->arch_info;
	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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	LOG_DEBUG("target->state: %s",
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		target_state_name(target));
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	enum reset_types jtag_reset_config = jtag_get_reset_config();
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	if (!(jtag_reset_config & RESET_HAS_SRST))
	{
		LOG_ERROR("Can't assert SRST");
		return ERROR_FAIL;
	}
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	if (target->reset_halt)
	{
		/* use hardware to catch reset */
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		jtag_set_end_state(TAP_IDLE);
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		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
	}
	else
	{
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		jtag_set_end_state(TAP_IDLE);
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		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
	}
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	if (strcmp(target->variant, "ejtag_srst") == 0)
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	{
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		uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
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		LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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	}
	else
	{
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		/* here we should issue a srst only, but we may have to assert trst as well */
		if (jtag_reset_config & RESET_SRST_PULLS_TRST)
		{
			jtag_add_reset(1, 1);
		}
		else
		{
			jtag_add_reset(0, 1);
		}
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	}
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	target->state = TARGET_RESET;
	jtag_add_sleep(50000);

	mips32_invalidate_core_regs(target);

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	if (target->reset_halt)
	{
		int retval;
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		if ((retval = target_halt(target)) != ERROR_OK)
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			return retval;
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	}
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	return ERROR_OK;
}

int mips_m4k_deassert_reset(target_t *target)
{
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	LOG_DEBUG("target->state: %s",
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		target_state_name(target));
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	/* deassert reset lines */
	jtag_add_reset(0, 0);
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	return ERROR_OK;
}

int mips_m4k_soft_reset_halt(struct target_s *target)
{
	/* TODO */
	return ERROR_OK;
}

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int mips_m4k_single_step_core(target_t *target)
{
	mips32_common_t *mips32 = target->arch_info;
	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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	/* configure single step mode */
	mips_ejtag_config_step(ejtag_info, 1);
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	/* disable interrupts while stepping */
	mips32_enable_interrupts(target, 0);
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	/* exit debug mode */
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	mips_ejtag_exit_debug(ejtag_info);
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	mips_m4k_debug_entry(target);
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	return ERROR_OK;
}

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int mips_m4k_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
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{
	mips32_common_t *mips32 = target->arch_info;
	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
	breakpoint_t *breakpoint = NULL;
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	uint32_t resume_pc;
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	if (target->state != TARGET_HALTED)
	{
		LOG_WARNING("target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}
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	if (!debug_execution)
	{
		target_free_all_working_areas(target);
		mips_m4k_enable_breakpoints(target);
		mips_m4k_enable_watchpoints(target);
	}
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	/* current = 1: continue on current pc, otherwise continue at <address> */
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	if (!current)
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	{
		buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
		mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
		mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
	}
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	resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
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	mips32_restore_context(target);
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	/* the front-end may request us not to handle breakpoints */
	if (handle_breakpoints)
	{
		/* Single step past breakpoint at current address */
		if ((breakpoint = breakpoint_find(target, resume_pc)))
		{
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			LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
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			mips_m4k_unset_breakpoint(target, breakpoint);
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			mips_m4k_single_step_core(target);
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			mips_m4k_set_breakpoint(target, breakpoint);
		}
	}
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	/* enable interrupts if we are running */
	mips32_enable_interrupts(target, !debug_execution);
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	/* exit debug mode */
	mips_ejtag_exit_debug(ejtag_info);
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	target->debug_reason = DBG_REASON_NOTHALTED;
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	/* registers are now invalid */
	mips32_invalidate_core_regs(target);
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	if (!debug_execution)
	{
		target->state = TARGET_RUNNING;
		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
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		LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
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	}
	else
	{
		target->state = TARGET_DEBUG_RUNNING;
		target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
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		LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
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	}
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	return ERROR_OK;
}

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int mips_m4k_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
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{
	/* get pointers to arch-specific information */
	mips32_common_t *mips32 = target->arch_info;
	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
	breakpoint_t *breakpoint = NULL;

	if (target->state != TARGET_HALTED)
	{
		LOG_WARNING("target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}

	/* current = 1: continue on current pc, otherwise continue at <address> */
	if (!current)
		buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
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	/* the front-end may request us not to handle breakpoints */
	if (handle_breakpoints)
		if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
			mips_m4k_unset_breakpoint(target, breakpoint);
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	/* restore context */
	mips32_restore_context(target);
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	/* configure single step mode */
	mips_ejtag_config_step(ejtag_info, 1);
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	target->debug_reason = DBG_REASON_SINGLESTEP;
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	target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
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	/* disable interrupts while stepping */
	mips32_enable_interrupts(target, 0);
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	/* exit debug mode */
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	mips_ejtag_exit_debug(ejtag_info);
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	/* registers are now invalid */
	mips32_invalidate_core_regs(target);
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	if (breakpoint)
		mips_m4k_set_breakpoint(target, breakpoint);

	LOG_DEBUG("target stepped ");
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	mips_m4k_debug_entry(target);
	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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	return ERROR_OK;
}

void mips_m4k_enable_breakpoints(struct target_s *target)
{
	breakpoint_t *breakpoint = target->breakpoints;
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	/* set any pending breakpoints */
	while (breakpoint)
	{
		if (breakpoint->set == 0)
			mips_m4k_set_breakpoint(target, breakpoint);
		breakpoint = breakpoint->next;
	}
}

int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
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	mips32_common_t *mips32 = target->arch_info;
	mips32_comparator_t * comparator_list = mips32->inst_break_list;
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	int retval;
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	if (breakpoint->set)
	{
		LOG_WARNING("breakpoint already set");
		return ERROR_OK;
	}
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	if (breakpoint->type == BKPT_HARD)
	{
		int bp_num = 0;
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		while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
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			bp_num++;
		if (bp_num >= mips32->num_inst_bpoints)
		{
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			LOG_DEBUG("ERROR Can not find free FP Comparator(bpid: %d)",
					  breakpoint->unique_id );
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			LOG_WARNING("ERROR Can not find free FP Comparator");
			exit(-1);
		}
		breakpoint->set = bp_num + 1;
		comparator_list[bp_num].used = 1;
		comparator_list[bp_num].bp_value = breakpoint->address;
		target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
		target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
		target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
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		LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "", 
				  breakpoint->unique_id,
				  bp_num, comparator_list[bp_num].bp_value);
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	}
	else if (breakpoint->type == BKPT_SOFT)
	{
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		LOG_DEBUG("bpid: %d", breakpoint->unique_id );
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		if (breakpoint->length == 4)
		{
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			uint32_t verify = 0xffffffff;
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			if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
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			{
				return retval;
			}
			if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
			{
				return retval;
			}
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			if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
			{
				return retval;
			}
			if (verify != MIPS32_SDBBP)
			{
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				LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
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				return ERROR_OK;
			}
		}
		else
		{
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			uint16_t verify = 0xffff;
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			if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
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			{
				return retval;
			}
			if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
			{
				return retval;
			}
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			if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
			{
				return retval;
			}
			if (verify != MIPS16_SDBBP)
			{
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				LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
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				return ERROR_OK;
			}
		}
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		breakpoint->set = 20; /* Any nice value but 0 */
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	}
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	return ERROR_OK;
}

int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
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	/* get pointers to arch-specific information */
	mips32_common_t *mips32 = target->arch_info;
	mips32_comparator_t * comparator_list = mips32->inst_break_list;
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	int retval;
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	if (!breakpoint->set)
	{
		LOG_WARNING("breakpoint not set");
		return ERROR_OK;
	}
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	if (breakpoint->type == BKPT_HARD)
	{
		int bp_num = breakpoint->set - 1;
		if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
		{
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			LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
					  breakpoint->unique_id);
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			return ERROR_OK;
		}
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		LOG_DEBUG("bpid: %d - releasing hw: %d",
				  breakpoint->unique_id,
				  bp_num );
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		comparator_list[bp_num].used = 0;
		comparator_list[bp_num].bp_value = 0;
		target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
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	}
	else
	{
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		/* restore original instruction (kept in target endianness) */
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		LOG_DEBUG("bpid: %d", breakpoint->unique_id);
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		if (breakpoint->length == 4)
		{
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			uint32_t current_instr;
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			/* check that user program has not modified breakpoint instruction */
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			if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
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			{
				return retval;
			}
			if (current_instr == MIPS32_SDBBP)
			{
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				if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
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				{
					return retval;
				}
			}
		}
		else
		{
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			uint16_t current_instr;
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			/* check that user program has not modified breakpoint instruction */
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			if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
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			{
				return retval;
			}
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			if (current_instr == MIPS16_SDBBP)
			{
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				if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
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				{
					return retval;
				}
			}
		}
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	}
	breakpoint->set = 0;
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	return ERROR_OK;
}

int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
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	if (breakpoint->type == BKPT_HARD)
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	{
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		if (mips32->num_inst_bpoints_avail < 1)
		{
			LOG_INFO("no hardware breakpoint available");
			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
		}
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		mips32->num_inst_bpoints_avail--;
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	}
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	mips_m4k_set_breakpoint(target, breakpoint);
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	return ERROR_OK;
}

int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
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	/* get pointers to arch-specific information */
	mips32_common_t *mips32 = target->arch_info;
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	if (target->state != TARGET_HALTED)
	{
		LOG_WARNING("target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}
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	if (breakpoint->set)
	{
		mips_m4k_unset_breakpoint(target, breakpoint);
	}
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	if (breakpoint->type == BKPT_HARD)
		mips32->num_inst_bpoints_avail++;
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	return ERROR_OK;
}

int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
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	mips32_common_t *mips32 = target->arch_info;
	mips32_comparator_t * comparator_list = mips32->data_break_list;
	int wp_num = 0;
	/*
	 * watchpoint enabled, ignore all byte lanes in value register
	 * and exclude both load and store accesses from  watchpoint
	 * condition evaluation
	*/
	int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE | 
                (0xff << EJTAG_DBCn_BLM_SHIFT);
	
	if (watchpoint->set)
	{
		LOG_WARNING("watchpoint already set");
		return ERROR_OK;
	}

	while(comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
		wp_num++;
	if (wp_num >= mips32->num_data_bpoints)
	{
		LOG_DEBUG("ERROR Can not find free FP Comparator");
		LOG_WARNING("ERROR Can not find free FP Comparator");
		exit(-1);
	}

	if (watchpoint->length != 4)
	{
		LOG_ERROR("Only watchpoints of length 4 are supported");
		return ERROR_TARGET_UNALIGNED_ACCESS;
	}

	if (watchpoint->address % 4)
	{
		LOG_ERROR("Watchpoints address should be word aligned");
		return ERROR_TARGET_UNALIGNED_ACCESS;
	}

	switch (watchpoint->rw)
	{
		case WPT_READ:
			enable &= ~EJTAG_DBCn_NOLB;
			break;
		case WPT_WRITE:
			enable &= ~EJTAG_DBCn_NOSB;
			break;
		case WPT_ACCESS:
			enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
			break;
		default:
			LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
	}

	watchpoint->set = wp_num + 1;
	comparator_list[wp_num].used = 1;
	comparator_list[wp_num].bp_value = watchpoint->address;
	target_write_u32(target, comparator_list[wp_num].reg_address, comparator_list[wp_num].bp_value);
	target_write_u32(target, comparator_list[wp_num].reg_address + 0x08, 0x00000000);
	target_write_u32(target, comparator_list[wp_num].reg_address + 0x10, 0x00000000);
	target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
	target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
	LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
	
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	return ERROR_OK;
}

int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
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	/* get pointers to arch-specific information */
	mips32_common_t *mips32 = target->arch_info;
	mips32_comparator_t * comparator_list = mips32->data_break_list;
	
	if (!watchpoint->set)
	{
		LOG_WARNING("watchpoint not set");
		return ERROR_OK;
	}

	int wp_num = watchpoint->set - 1;
	if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints))
	{
		LOG_DEBUG("Invalid FP Comparator number in watchpoint");
		return ERROR_OK;
	}
	comparator_list[wp_num].used = 0;
	comparator_list[wp_num].bp_value = 0;
	target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, 0);
	watchpoint->set = 0;

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	return ERROR_OK;
}

int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
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	mips32_common_t *mips32 = target->arch_info;

	if (mips32->num_data_bpoints_avail < 1)
	{
		LOG_INFO("no hardware watchpoints available");
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}
		
	mips32->num_data_bpoints_avail--;

	mips_m4k_set_watchpoint(target, watchpoint);
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	return ERROR_OK;
}

int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
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	/* get pointers to arch-specific information */
	mips32_common_t *mips32 = target->arch_info;

	if (target->state != TARGET_HALTED)
	{
		LOG_WARNING("target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}

	if (watchpoint->set)
	{
		mips_m4k_unset_watchpoint(target, watchpoint);
	}

	mips32->num_data_bpoints_avail++;

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	return ERROR_OK;
}

void mips_m4k_enable_watchpoints(struct target_s *target)
{
	watchpoint_t *watchpoint = target->watchpoints;
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	/* set any pending watchpoints */
	while (watchpoint)
	{
		if (watchpoint->set == 0)
			mips_m4k_set_watchpoint(target, watchpoint);
		watchpoint = watchpoint->next;
	}
}

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int mips_m4k_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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{
	mips32_common_t *mips32 = target->arch_info;
	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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	LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
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	if (target->state != TARGET_HALTED)
	{
		LOG_WARNING("target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}

	/* sanitize arguments */
	if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
		return ERROR_INVALID_ARGUMENTS;

	if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
		return ERROR_TARGET_UNALIGNED_ACCESS;
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	/* if noDMA off, use DMAACC mode for memory read */
	int retval;
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	if (ejtag_info->impcode & EJTAG_IMP_NODMA)
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		retval = mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
	else
		retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
	if (ERROR_OK != retval)
		return retval;
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	/* TAP data register is loaded LSB first (little endian) */
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	if (target->endianness == TARGET_BIG_ENDIAN)
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	{
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		uint32_t i, t32;
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		uint16_t t16;
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		for (i = 0; i < (count*size); i += size)
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		{
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			switch (size)
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			{
				case 4:
					t32 = le_to_h_u32(&buffer[i]);
					h_u32_to_be(&buffer[i], t32);
					break;
				case 2:
					t16 = le_to_h_u16(&buffer[i]);
					h_u16_to_be(&buffer[i], t16);
					break;
			}
		}
	}
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	return ERROR_OK;
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}

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int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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{
	mips32_common_t *mips32 = target->arch_info;
	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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	LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
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	if (target->state != TARGET_HALTED)
	{
		LOG_WARNING("target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}

	/* sanitize arguments */
	if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
		return ERROR_INVALID_ARGUMENTS;

	if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
		return ERROR_TARGET_UNALIGNED_ACCESS;
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	/* TAP data register is loaded LSB first (little endian) */
	if (target->endianness == TARGET_BIG_ENDIAN)
	{
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		uint32_t i, t32;
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		uint16_t t16;
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		for (i = 0; i < (count*size); i += size)
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		{
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			switch (size)
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			{
				case 4:
					t32 = be_to_h_u32(&buffer[i]);
					h_u32_to_le(&buffer[i], t32);
					break;
				case 2:
					t16 = be_to_h_u16(&buffer[i]);
					h_u16_to_le(&buffer[i], t16);
					break;
			}
		}
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	}
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	/* if noDMA off, use DMAACC mode for memory write */
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	if (ejtag_info->impcode & EJTAG_IMP_NODMA)
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		return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
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	else
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		return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
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}

int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
{
	int retval;
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	retval = mips32_register_commands(cmd_ctx);
	return retval;
}

int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
	mips32_build_reg_cache(target);
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	return ERROR_OK;
}

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int mips_m4k_quit(void)
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{
	return ERROR_OK;
}

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int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
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{
	mips32_common_t *mips32 = &mips_m4k->mips32_common;
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	mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
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	/* initialize mips4k specific info */
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	mips32_init_arch_info(target, mips32, tap);
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	mips32->arch_info = mips_m4k;
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	return ERROR_OK;
}

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int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
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{
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	mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
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	mips_m4k_init_arch_info(target, mips_m4k, target->tap);
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	return ERROR_OK;
}

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int mips_m4k_examine(struct target_s *target)
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{
	int retval;
	mips32_common_t *mips32 = target->arch_info;
	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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	uint32_t idcode = 0;
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	if (!target_was_examined(target))
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	{
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		mips_ejtag_get_idcode(ejtag_info, &idcode);
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		ejtag_info->idcode = idcode;
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		if (((idcode >> 1) & 0x7FF) == 0x29)
		{
			/* we are using a pic32mx so select ejtag port
			 * as it is not selected by default */
			mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
			LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
		}
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	}
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	/* init rest of ejtag interface */
	if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
		return retval;
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	if ((retval = mips32_examine(target)) != ERROR_OK)
		return retval;
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	return ERROR_OK;
}

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int mips_m4k_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
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{
	return mips_m4k_write_memory(target, address, 4, count, buffer);
}
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int mips_m4k_checksum_memory(target_t *target, uint32_t address, uint32_t size, uint32_t *checksum)
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{
	return ERROR_FAIL; /* use bulk read method */
}