nand.c 41.3 KB
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/***************************************************************************
 *   Copyright (C) 2007 by Dominic Rath                                    *
 *   Dominic.Rath@gmx.de                                                   *
 *                                                                         *
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 *   Partially based on drivers/mtd/nand_ids.c from Linux.                 *
 *   Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de>               *
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 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 ***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "nand.h"
#include "time_support.h"
#include "fileio.h"
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static int nand_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
//static int nand_read_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size);
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static int nand_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
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/* NAND flash controller
 */
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extern nand_flash_controller_t davinci_nand_controller;
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extern nand_flash_controller_t lpc3180_nand_controller;
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extern nand_flash_controller_t orion_nand_controller;
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extern nand_flash_controller_t s3c2410_nand_controller;
extern nand_flash_controller_t s3c2412_nand_controller;
extern nand_flash_controller_t s3c2440_nand_controller;
extern nand_flash_controller_t s3c2443_nand_controller;
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extern nand_flash_controller_t imx31_nand_flash_controller;
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/* extern nand_flash_controller_t boundary_scan_nand_controller; */

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static nand_flash_controller_t *nand_flash_controllers[] =
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{
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	&davinci_nand_controller,
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	&lpc3180_nand_controller,
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	&orion_nand_controller,
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	&s3c2410_nand_controller,
	&s3c2412_nand_controller,
	&s3c2440_nand_controller,
	&s3c2443_nand_controller,
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 	&imx31_nand_flash_controller,
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/*	&boundary_scan_nand_controller, */
	NULL
};

/* configured NAND devices and NAND Flash command handler */
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static nand_device_t *nand_devices = NULL;
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static command_t *nand_cmd;

/*	Chip ID list
 *
 *	Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
 *	options
 *
 *	Pagesize; 0, 256, 512
 *	0	get this information from the extended chip ID
 *	256	256 Byte page size
 *	512	512 Byte page size
 */
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static nand_info_t nand_flash_ids[] =
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{
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	/* start "museum" IDs */
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	{"NAND 1MiB 5V 8-bit",		0x6e, 256, 1, 0x1000, 0},
	{"NAND 2MiB 5V 8-bit",		0x64, 256, 2, 0x1000, 0},
	{"NAND 4MiB 5V 8-bit",		0x6b, 512, 4, 0x2000, 0},
	{"NAND 1MiB 3,3V 8-bit",	0xe8, 256, 1, 0x1000, 0},
	{"NAND 1MiB 3,3V 8-bit",	0xec, 256, 1, 0x1000, 0},
	{"NAND 2MiB 3,3V 8-bit",	0xea, 256, 2, 0x1000, 0},
	{"NAND 4MiB 3,3V 8-bit",	0xd5, 512, 4, 0x2000, 0},
	{"NAND 4MiB 3,3V 8-bit",	0xe3, 512, 4, 0x2000, 0},
	{"NAND 4MiB 3,3V 8-bit",	0xe5, 512, 4, 0x2000, 0},
	{"NAND 8MiB 3,3V 8-bit",	0xd6, 512, 8, 0x2000, 0},

	{"NAND 8MiB 1,8V 8-bit",	0x39, 512, 8, 0x2000, 0},
	{"NAND 8MiB 3,3V 8-bit",	0xe6, 512, 8, 0x2000, 0},
	{"NAND 8MiB 1,8V 16-bit",	0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
	{"NAND 8MiB 3,3V 16-bit",	0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
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	/* end "museum" IDs */
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	{"NAND 16MiB 1,8V 8-bit",	0x33, 512, 16, 0x4000, 0},
	{"NAND 16MiB 3,3V 8-bit",	0x73, 512, 16, 0x4000, 0},
	{"NAND 16MiB 1,8V 16-bit",	0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
	{"NAND 16MiB 3,3V 16-bit",	0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},

	{"NAND 32MiB 1,8V 8-bit",	0x35, 512, 32, 0x4000, 0},
	{"NAND 32MiB 3,3V 8-bit",	0x75, 512, 32, 0x4000, 0},
	{"NAND 32MiB 1,8V 16-bit",	0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
	{"NAND 32MiB 3,3V 16-bit",	0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},

	{"NAND 64MiB 1,8V 8-bit",	0x36, 512, 64, 0x4000, 0},
	{"NAND 64MiB 3,3V 8-bit",	0x76, 512, 64, 0x4000, 0},
	{"NAND 64MiB 1,8V 16-bit",	0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
	{"NAND 64MiB 3,3V 16-bit",	0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},

	{"NAND 128MiB 1,8V 8-bit",	0x78, 512, 128, 0x4000, 0},
	{"NAND 128MiB 1,8V 8-bit",	0x39, 512, 128, 0x4000, 0},
	{"NAND 128MiB 3,3V 8-bit",	0x79, 512, 128, 0x4000, 0},
	{"NAND 128MiB 1,8V 16-bit",	0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
	{"NAND 128MiB 1,8V 16-bit",	0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
	{"NAND 128MiB 3,3V 16-bit",	0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
	{"NAND 128MiB 3,3V 16-bit",	0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},

	{"NAND 256MiB 3,3V 8-bit",	0x71, 512, 256, 0x4000, 0},

	{"NAND 64MiB 1,8V 8-bit",	0xA2, 0,  64, 0, LP_OPTIONS},
	{"NAND 64MiB 3,3V 8-bit",	0xF2, 0,  64, 0, LP_OPTIONS},
	{"NAND 64MiB 1,8V 16-bit",	0xB2, 0,  64, 0, LP_OPTIONS16},
	{"NAND 64MiB 3,3V 16-bit",	0xC2, 0,  64, 0, LP_OPTIONS16},

	{"NAND 128MiB 1,8V 8-bit",	0xA1, 0, 128, 0, LP_OPTIONS},
	{"NAND 128MiB 3,3V 8-bit",	0xF1, 0, 128, 0, LP_OPTIONS},
	{"NAND 128MiB 1,8V 16-bit",	0xB1, 0, 128, 0, LP_OPTIONS16},
	{"NAND 128MiB 3,3V 16-bit",	0xC1, 0, 128, 0, LP_OPTIONS16},

	{"NAND 256MiB 1,8V 8-bit",	0xAA, 0, 256, 0, LP_OPTIONS},
	{"NAND 256MiB 3,3V 8-bit",	0xDA, 0, 256, 0, LP_OPTIONS},
	{"NAND 256MiB 1,8V 16-bit",	0xBA, 0, 256, 0, LP_OPTIONS16},
	{"NAND 256MiB 3,3V 16-bit",	0xCA, 0, 256, 0, LP_OPTIONS16},

	{"NAND 512MiB 1,8V 8-bit",	0xAC, 0, 512, 0, LP_OPTIONS},
	{"NAND 512MiB 3,3V 8-bit",	0xDC, 0, 512, 0, LP_OPTIONS},
	{"NAND 512MiB 1,8V 16-bit",	0xBC, 0, 512, 0, LP_OPTIONS16},
	{"NAND 512MiB 3,3V 16-bit",	0xCC, 0, 512, 0, LP_OPTIONS16},

	{"NAND 1GiB 1,8V 8-bit",	0xA3, 0, 1024, 0, LP_OPTIONS},
	{"NAND 1GiB 3,3V 8-bit",	0xD3, 0, 1024, 0, LP_OPTIONS},
	{"NAND 1GiB 1,8V 16-bit",	0xB3, 0, 1024, 0, LP_OPTIONS16},
	{"NAND 1GiB 3,3V 16-bit",	0xC3, 0, 1024, 0, LP_OPTIONS16},

	{"NAND 2GiB 1,8V 8-bit",	0xA5, 0, 2048, 0, LP_OPTIONS},
	{"NAND 2GiB 3,3V 8-bit",	0xD5, 0, 2048, 0, LP_OPTIONS},
	{"NAND 2GiB 1,8V 16-bit",	0xB5, 0, 2048, 0, LP_OPTIONS16},
	{"NAND 2GiB 3,3V 16-bit",	0xC5, 0, 2048, 0, LP_OPTIONS16},

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	{NULL, 0, 0, 0, 0, 0 }
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};

/* Manufacturer ID list
 */
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static nand_manufacturer_t nand_manuf_ids[] =
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{
	{0x0, "unknown"},
	{NAND_MFR_TOSHIBA, "Toshiba"},
	{NAND_MFR_SAMSUNG, "Samsung"},
	{NAND_MFR_FUJITSU, "Fujitsu"},
	{NAND_MFR_NATIONAL, "National"},
	{NAND_MFR_RENESAS, "Renesas"},
	{NAND_MFR_STMICRO, "ST Micro"},
	{NAND_MFR_HYNIX, "Hynix"},
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	{NAND_MFR_MICRON, "Micron"},
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	{0x0, NULL},
};

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/*
 * Define default oob placement schemes for large and small page devices
 */

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#if 0
static nand_ecclayout_t nand_oob_8 = {
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	.eccbytes = 3,
	.eccpos = {0, 1, 2},
	.oobfree = {
		{.offset = 3,
		 .length = 2},
		{.offset = 6,
		 .length = 2}}
};
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#endif
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static nand_ecclayout_t nand_oob_16 = {
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	.eccbytes = 6,
	.eccpos = {0, 1, 2, 3, 6, 7},
	.oobfree = {
		{.offset = 8,
		 . length = 8}}
};

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static nand_ecclayout_t nand_oob_64 = {
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	.eccbytes = 24,
	.eccpos = {
		   40, 41, 42, 43, 44, 45, 46, 47,
		   48, 49, 50, 51, 52, 53, 54, 55,
		   56, 57, 58, 59, 60, 61, 62, 63},
	.oobfree = {
		{.offset = 2,
		 .length = 38}}
};

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/* nand device <nand_controller> [controller options]
 */
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static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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{
	int i;
	int retval;
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	if (argc < 1)
	{
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		LOG_WARNING("incomplete flash device nand configuration");
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		return ERROR_FLASH_BANK_INVALID;
	}
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	for (i = 0; nand_flash_controllers[i]; i++)
	{
		nand_device_t *p, *c;
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		if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
		{
			/* register flash specific commands */
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			if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
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			{
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				LOG_ERROR("couldn't register '%s' commands", args[0]);
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				return retval;
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			}
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			c = malloc(sizeof(nand_device_t));

			c->controller = nand_flash_controllers[i];
			c->controller_priv = NULL;
			c->manufacturer = NULL;
			c->device = NULL;
			c->bus_width = 0;
			c->address_cycles = 0;
			c->page_size = 0;
			c->use_raw = 0;
			c->next = NULL;

			if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
			{
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				LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
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				free(c);
				return ERROR_OK;
			}
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			/* put NAND device in linked list */
			if (nand_devices)
			{
				/* find last flash device */
				for (p = nand_devices; p && p->next; p = p->next);
				if (p)
					p->next = c;
			}
			else
			{
				nand_devices = c;
			}
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			return ERROR_OK;
		}
	}

	/* no valid NAND controller was found (i.e. the configuration option,
	 * didn't match one of the compiled-in controllers)
	 */
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	LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
	LOG_ERROR("compiled-in NAND flash controllers:");
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	for (i = 0; nand_flash_controllers[i]; i++)
	{
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		LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
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	}
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	return ERROR_OK;
}

int nand_register_commands(struct command_context_s *cmd_ctx)
{
	nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
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	register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
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	return ERROR_OK;
}

nand_device_t *get_nand_device_by_num(int num)
{
	nand_device_t *p;
	int i = 0;

	for (p = nand_devices; p; p = p->next)
	{
		if (i++ == num)
		{
			return p;
		}
	}
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	return NULL;
}

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int nand_command_get_device_by_num(struct command_context_s *cmd_ctx,
		char *str, nand_device_t **device)
{
	unsigned num;
	COMMAND_PARSE_NUMBER(uint, str, num);
	*device = get_nand_device_by_num(num);
	if (!*device) {
		command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", str);
		return ERROR_INVALID_ARGUMENTS;
	}
	return ERROR_OK;
}

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static int nand_build_bbt(struct nand_device_s *device, int first, int last)
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{
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	uint32_t page = 0x0;
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	int i;
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	uint8_t oob[6];
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	if ((first < 0) || (first >= device->num_blocks))
		first = 0;
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	if ((last >= device->num_blocks) || (last == -1))
		last = device->num_blocks - 1;
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	for (i = first; i < last; i++)
	{
		nand_read_page(device, page, NULL, 0, oob, 6);
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		if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
			|| (((device->page_size == 512) && (oob[5] != 0xff)) ||
				((device->page_size == 2048) && (oob[0] != 0xff))))
		{
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			LOG_WARNING("bad block: %i", i);
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			device->blocks[i].is_bad = 1;
		}
		else
		{
			device->blocks[i].is_bad = 0;
		}
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		page += (device->erase_size / device->page_size);
	}
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	return ERROR_OK;
}

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int nand_read_status(struct nand_device_s *device, uint8_t *status)
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{
	if (!device->device)
		return ERROR_NAND_DEVICE_NOT_PROBED;
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	/* Send read status command */
	device->controller->command(device, NAND_CMD_STATUS);
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	alive_sleep(1);
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	/* read status */
	if (device->device->options & NAND_BUSWIDTH_16)
	{
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		uint16_t data;
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		device->controller->read_data(device, &data);
		*status = data & 0xff;
	}
	else
	{
		device->controller->read_data(device, status);
	}
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	return ERROR_OK;
}

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static int nand_poll_ready(struct nand_device_s *device, int timeout)
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{
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	uint8_t status;
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	device->controller->command(device, NAND_CMD_STATUS);
	do {
		if (device->device->options & NAND_BUSWIDTH_16) {
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			uint16_t data;
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			device->controller->read_data(device, &data);
			status = data & 0xff;
		} else {
			device->controller->read_data(device, &status);
		}
		if (status & NAND_STATUS_READY)
			break;
		alive_sleep(1);
	} while (timeout--);

	return (status & NAND_STATUS_READY) != 0;
}

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int nand_probe(struct nand_device_s *device)
{
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	uint8_t manufacturer_id, device_id;
	uint8_t id_buff[6];
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	int retval;
	int i;

	/* clear device data */
	device->device = NULL;
	device->manufacturer = NULL;
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	/* clear device parameters */
	device->bus_width = 0;
	device->address_cycles = 0;
	device->page_size = 0;
	device->erase_size = 0;
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	/* initialize controller (device parameters are zero, use controller default) */
	if ((retval = device->controller->init(device) != ERROR_OK))
	{
		switch (retval)
		{
			case ERROR_NAND_OPERATION_FAILED:
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				LOG_DEBUG("controller initialization failed");
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				return ERROR_NAND_OPERATION_FAILED;
			case ERROR_NAND_OPERATION_NOT_SUPPORTED:
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				LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
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				return ERROR_NAND_OPERATION_FAILED;
			default:
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				LOG_ERROR("BUG: unknown controller initialization failure");
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				return ERROR_NAND_OPERATION_FAILED;
		}
	}
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	device->controller->command(device, NAND_CMD_RESET);
	device->controller->reset(device);

	device->controller->command(device, NAND_CMD_READID);
	device->controller->address(device, 0x0);
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	if (device->bus_width == 8)
	{
		device->controller->read_data(device, &manufacturer_id);
		device->controller->read_data(device, &device_id);
	}
	else
	{
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		uint16_t data_buf;
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		device->controller->read_data(device, &data_buf);
		manufacturer_id = data_buf & 0xff;
		device->controller->read_data(device, &data_buf);
		device_id = data_buf & 0xff;
	}
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	for (i = 0; nand_flash_ids[i].name; i++)
	{
		if (nand_flash_ids[i].id == device_id)
		{
			device->device = &nand_flash_ids[i];
			break;
		}
	}
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	for (i = 0; nand_manuf_ids[i].name; i++)
	{
		if (nand_manuf_ids[i].id == manufacturer_id)
		{
			device->manufacturer = &nand_manuf_ids[i];
			break;
		}
	}
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	if (!device->manufacturer)
	{
		device->manufacturer = &nand_manuf_ids[0];
		device->manufacturer->id = manufacturer_id;
	}
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	if (!device->device)
	{
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		LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
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			manufacturer_id, device_id);
		return ERROR_NAND_OPERATION_FAILED;
	}
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	LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
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	/* initialize device parameters */
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	/* bus width */
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	if (device->device->options & NAND_BUSWIDTH_16)
		device->bus_width = 16;
	else
		device->bus_width = 8;

	/* Do we need extended device probe information? */
	if (device->device->page_size == 0 ||
	    device->device->erase_size == 0)
	{
		if (device->bus_width == 8)
		{
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			device->controller->read_data(device, id_buff + 3);
			device->controller->read_data(device, id_buff + 4);
			device->controller->read_data(device, id_buff + 5);
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		}
		else
		{
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			uint16_t data_buf;
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			device->controller->read_data(device, &data_buf);
			id_buff[3] = data_buf;

			device->controller->read_data(device, &data_buf);
			id_buff[4] = data_buf;

			device->controller->read_data(device, &data_buf);
			id_buff[5] = data_buf >> 8;
		}
	}
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	/* page size */
	if (device->device->page_size == 0)
	{
		device->page_size = 1 << (10 + (id_buff[4] & 3));
	}
	else if (device->device->page_size == 256)
	{
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		LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
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		return ERROR_NAND_OPERATION_FAILED;
	}
	else
	{
		device->page_size = device->device->page_size;
	}
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	/* number of address cycles */
	if (device->page_size <= 512)
	{
		/* small page devices */
		if (device->device->chip_size <= 32)
			device->address_cycles = 3;
		else if (device->device->chip_size <= 8*1024)
			device->address_cycles = 4;
		else
		{
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			LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
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			device->address_cycles = 5;
		}
	}
	else
	{
		/* large page devices */
		if (device->device->chip_size <= 128)
			device->address_cycles = 4;
		else if (device->device->chip_size <= 32*1024)
			device->address_cycles = 5;
		else
		{
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			LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
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			device->address_cycles = 6;
		}
	}
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	/* erase size */
	if (device->device->erase_size == 0)
	{
		switch ((id_buff[4] >> 4) & 3) {
		case 0:
			device->erase_size = 64 << 10;
			break;
		case 1:
			device->erase_size = 128 << 10;
			break;
		case 2:
			device->erase_size = 256 << 10;
			break;
		case 3:
			device->erase_size =512 << 10;
			break;
		}
	}
	else
	{
		device->erase_size = device->device->erase_size;
	}
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	/* initialize controller, but leave parameters at the controllers default */
	if ((retval = device->controller->init(device) != ERROR_OK))
	{
		switch (retval)
		{
			case ERROR_NAND_OPERATION_FAILED:
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				LOG_DEBUG("controller initialization failed");
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				return ERROR_NAND_OPERATION_FAILED;
			case ERROR_NAND_OPERATION_NOT_SUPPORTED:
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				LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
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					device->bus_width, device->address_cycles, device->page_size);
				return ERROR_NAND_OPERATION_FAILED;
			default:
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				LOG_ERROR("BUG: unknown controller initialization failure");
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				return ERROR_NAND_OPERATION_FAILED;
		}
	}
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	device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
	device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
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	for (i = 0; i < device->num_blocks; i++)
	{
		device->blocks[i].size = device->erase_size;
		device->blocks[i].offset = i * device->erase_size;
		device->blocks[i].is_erased = -1;
		device->blocks[i].is_bad = -1;
	}
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	return ERROR_OK;
}

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static int nand_erase(struct nand_device_s *device, int first_block, int last_block)
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{
	int i;
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	uint32_t page;
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	uint8_t status;
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	int retval;
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	if (!device->device)
		return ERROR_NAND_DEVICE_NOT_PROBED;
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	if ((first_block < 0) || (last_block > device->num_blocks))
		return ERROR_INVALID_ARGUMENTS;
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	/* make sure we know if a block is bad before erasing it */
	for (i = first_block; i <= last_block; i++)
	{
		if (device->blocks[i].is_bad == -1)
		{
			nand_build_bbt(device, i, last_block);
			break;
		}
	}
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	for (i = first_block; i <= last_block; i++)
	{
		/* Send erase setup command */
		device->controller->command(device, NAND_CMD_ERASE1);
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		page = i * (device->erase_size / device->page_size);
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		/* Send page address */
		if (device->page_size <= 512)
		{
			/* row */
			device->controller->address(device, page & 0xff);
			device->controller->address(device, (page >> 8) & 0xff);
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			/* 3rd cycle only on devices with more than 32 MiB */
			if (device->address_cycles >= 4)
				device->controller->address(device, (page >> 16) & 0xff);
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			/* 4th cycle only on devices with more than 8 GiB */
			if (device->address_cycles >= 5)
				device->controller->address(device, (page >> 24) & 0xff);
		}
		else
		{
			/* row */
			device->controller->address(device, page & 0xff);
			device->controller->address(device, (page >> 8) & 0xff);
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			/* 3rd cycle only on devices with more than 128 MiB */
			if (device->address_cycles >= 5)
				device->controller->address(device, (page >> 16) & 0xff);
		}
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		/* Send erase confirm command */
		device->controller->command(device, NAND_CMD_ERASE2);
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		retval = device->controller->nand_ready ?
				device->controller->nand_ready(device, 1000) :
				nand_poll_ready(device, 1000);
		if (!retval) {
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			LOG_ERROR("timeout waiting for NAND flash block erase to complete");
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			return ERROR_NAND_OPERATION_TIMEOUT;
		}
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		if ((retval = nand_read_status(device, &status)) != ERROR_OK)
		{
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			LOG_ERROR("couldn't read status");
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			return ERROR_NAND_OPERATION_FAILED;
		}
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		if (status & 0x1)
		{
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			LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
					(device->blocks[i].is_bad == 1)
						? "bad " : "",
					i, status);
			/* continue; other blocks might still be erasable */
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		}
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		device->blocks[i].is_erased = 1;
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	}
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	return ERROR_OK;
}

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#if 0
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static int nand_read_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size)
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{
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	uint8_t *page;
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	if (!device->device)
		return ERROR_NAND_DEVICE_NOT_PROBED;
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	if (address % device->page_size)
	{
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		LOG_ERROR("reads need to be page aligned");
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		return ERROR_NAND_OPERATION_FAILED;
	}
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	page = malloc(device->page_size);
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	while (data_size > 0)
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	{
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		uint32_t thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
		uint32_t page_address;
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		page_address = address / device->page_size;
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		nand_read_page(device, page_address, page, device->page_size, NULL, 0);

		memcpy(data, page, thisrun_size);
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		address += thisrun_size;
		data += thisrun_size;
		data_size -= thisrun_size;
	}
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	free(page);
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	return ERROR_OK;
}

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static int nand_write_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size)
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{
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	uint8_t *page;
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	if (!device->device)
		return ERROR_NAND_DEVICE_NOT_PROBED;
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	if (address % device->page_size)
	{
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		LOG_ERROR("writes need to be page aligned");
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		return ERROR_NAND_OPERATION_FAILED;
	}
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	page = malloc(device->page_size);
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	while (data_size > 0)
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	{
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		uint32_t thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
		uint32_t page_address;
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		memset(page, 0xff, device->page_size);
		memcpy(page, data, thisrun_size);
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		page_address = address / device->page_size;
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		nand_write_page(device, page_address, page, device->page_size, NULL, 0);
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		address += thisrun_size;
		data += thisrun_size;
		data_size -= thisrun_size;
	}
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	free(page);
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	return ERROR_OK;
}
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#endif
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int nand_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
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{
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	uint32_t block;
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	if (!device->device)
		return ERROR_NAND_DEVICE_NOT_PROBED;
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	block = page / (device->erase_size / device->page_size);
	if (device->blocks[block].is_erased == 1)
		device->blocks[block].is_erased = 0;

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	if (device->use_raw || device->controller->write_page == NULL)
		return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
	else
		return device->controller->write_page(device, page, data, data_size, oob, oob_size);
}

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static int nand_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
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{
	if (!device->device)
		return ERROR_NAND_DEVICE_NOT_PROBED;
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	if (device->use_raw || device->controller->read_page == NULL)
		return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
	else
		return device->controller->read_page(device, page, data, data_size, oob, oob_size);
}

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int nand_read_page_raw(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
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{
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	uint32_t i;
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	if (!device->device)
		return ERROR_NAND_DEVICE_NOT_PROBED;

	if (device->page_size <= 512)
	{
		/* small page device */
		if (data)
			device->controller->command(device, NAND_CMD_READ0);
		else
			device->controller->command(device, NAND_CMD_READOOB);
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		/* column (always 0, we start at the beginning of a page/OOB area) */
		device->controller->address(device, 0x0);
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		/* row */
		device->controller->address(device, page & 0xff);
		device->controller->address(device, (page >> 8) & 0xff);
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		/* 4th cycle only on devices with more than 32 MiB */
		if (device->address_cycles >= 4)
			device->controller->address(device, (page >> 16) & 0xff);

		/* 5th cycle only on devices with more than 8 GiB */
		if (device->address_cycles >= 5)
			device->controller->address(device, (page >> 24) & 0xff);
	}
	else
	{
		/* large page device */
		device->controller->command(device, NAND_CMD_READ0);
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		/* column (0 when we start at the beginning of a page,
		 * or 2048 for the beginning of OOB area)
		 */
		device->controller->address(device, 0x0);
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		if (data)
			device->controller->address(device, 0x0);
		else
			device->controller->address(device, 0x8);
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		/* row */
		device->controller->address(device, page & 0xff);
		device->controller->address(device, (page >> 8) & 0xff);

		/* 5th cycle only on devices with more than 128 MiB */
		if (device->address_cycles >= 5)
			device->controller->address(device, (page >> 16) & 0xff);

		/* large page devices need a start command */
		device->controller->command(device, NAND_CMD_READSTART);
	}
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	if (device->controller->nand_ready) {
		if (!device->controller->nand_ready(device, 100))
			return ERROR_NAND_OPERATION_TIMEOUT;
	} else {
		alive_sleep(1);
	}
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	if (data)
	{
		if (device->controller->read_block_data != NULL)
			(device->controller->read_block_data)(device, data, data_size);
		else
		{
			for (i = 0; i < data_size;)
			{
				if (device->device->options & NAND_BUSWIDTH_16)
				{
					device->controller->read_data(device, data);
					data += 2;
					i += 2;
				}
				else
				{
					device->controller->read_data(device, data);
					data += 1;
					i += 1;
				}
			}
		}
	}
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	if (oob)
	{
		if (device->controller->read_block_data != NULL)
			(device->controller->read_block_data)(device, oob, oob_size);
		else
		{
			for (i = 0; i < oob_size;)
			{
				if (device->device->options & NAND_BUSWIDTH_16)
				{
					device->controller->read_data(device, oob);
					oob += 2;
					i += 2;
				}
				else
				{
					device->controller->read_data(device, oob);
					oob += 1;
					i += 1;
				}
			}
		}
	}
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	return ERROR_OK;
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}

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int nand_write_page_raw(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
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{
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	uint32_t i;
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	int retval;
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	uint8_t status;
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	if (!device->device)
		return ERROR_NAND_DEVICE_NOT_PROBED;

	device->controller->command(device, NAND_CMD_SEQIN);
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	if (device->page_size <= 512)
	{
		/* column (always 0, we start at the beginning of a page/OOB area) */
		device->controller->address(device, 0x0);
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		/* row */
		device->controller->address(device, page & 0xff);
		device->controller->address(device, (page >> 8) & 0xff);
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		/* 4th cycle only on devices with more than 32 MiB */
		if (device->address_cycles >= 4)
			device->controller->address(device, (page >> 16) & 0xff);

		/* 5th cycle only on devices with more than 8 GiB */
		if (device->address_cycles >= 5)
			device->controller->address(device, (page >> 24) & 0xff);
	}
	else
	{
		/* column (0 when we start at the beginning of a page,
		 * or 2048 for the beginning of OOB area)
		 */
		device->controller->address(device, 0x0);
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		if (data)
			device->controller->address(device, 0x0);
		else
			device->controller->address(device, 0x8);
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		/* row */
		device->controller->address(device, page & 0xff);
		device->controller->address(device, (page >> 8) & 0xff);

		/* 5th cycle only on devices with more than 128 MiB */
		if (device->address_cycles >= 5)
			device->controller->address(device, (page >> 16) & 0xff);
	}
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	if (data)
	{
		if (device->controller->write_block_data != NULL)
			(device->controller->write_block_data)(device, data, data_size);
		else
		{
			for (i = 0; i < data_size;)
			{
				if (device->device->options & NAND_BUSWIDTH_16)
				{
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					uint16_t data_buf = le_to_h_u16(data);
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					device->controller->write_data(device, data_buf);
					data += 2;
					i += 2;
				}
				else
				{
					device->controller->write_data(device, *data);
					data += 1;
					i += 1;
				}
			}
		}
	}
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	if (oob)
	{
		if (device->controller->write_block_data != NULL)
			(device->controller->write_block_data)(device, oob, oob_size);
		else
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