str9x.c 18.5 KB
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/***************************************************************************
 *   Copyright (C) 2005 by Dominic Rath                                    *
 *   Dominic.Rath@gmx.de                                                   *
 *                                                                         *
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 *   Copyright (C) 2008 by Spencer Oliver                                  *
 *   spen@spen-soft.co.uk                                                  *
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 *
 *   Copyright (C) 2008 by Oyvind Harboe                                   *
 *   oyvind.harboe@zylin.com                                               *
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 *                                                                         *
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 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 ***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "str9x.h"
#include "arm966e.h"


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static uint32_t bank1start = 0x00080000;
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static int str9x_register_commands(struct command_context_s *cmd_ctx);
static int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int str9x_erase(struct flash_bank_s *bank, int first, int last);
static int str9x_protect(struct flash_bank_s *bank, int set, int first, int last);
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static int str9x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
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static int str9x_probe(struct flash_bank_s *bank);
//static int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
static int str9x_protect_check(struct flash_bank_s *bank);
static int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size);
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static int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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flash_driver_t str9x_flash =
{
	.name = "str9x",
	.register_commands = str9x_register_commands,
	.flash_bank_command = str9x_flash_bank_command,
	.erase = str9x_erase,
	.protect = str9x_protect,
	.write = str9x_write,
	.probe = str9x_probe,
	.auto_probe = str9x_probe,
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	.erase_check = default_flash_blank_check,
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	.protect_check = str9x_protect_check,
	.info = str9x_info
};

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static int str9x_register_commands(struct command_context_s *cmd_ctx)
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{
	command_t *str9x_cmd = register_command(cmd_ctx, NULL, "str9x", NULL, COMMAND_ANY, NULL);
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	register_command(cmd_ctx, str9x_cmd, "flash_config", str9x_handle_flash_config_command, COMMAND_EXEC,
					 "configure str9 flash controller");
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	return ERROR_OK;
}

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static int str9x_build_block_list(struct flash_bank_s *bank)
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{
	str9x_flash_bank_t *str9x_info = bank->driver_priv;
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	int i;
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	int num_sectors;
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	int b0_sectors = 0, b1_sectors = 0;
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	uint32_t offset = 0;
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	/* set if we have large flash str9 */
	str9x_info->variant = 0;
	str9x_info->bank1 = 0;
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	switch (bank->size)
	{
		case (256 * 1024):
			b0_sectors = 4;
			break;
		case (512 * 1024):
			b0_sectors = 8;
			break;
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		case (1024 * 1024):
			bank1start = 0x00100000;
			str9x_info->variant = 1;
			b0_sectors = 16;
			break;
		case (2048 * 1024):
			bank1start = 0x00200000;
			str9x_info->variant = 1;
			b0_sectors = 32;
			break;
		case (128 * 1024):
			str9x_info->variant = 1;
			str9x_info->bank1 = 1;
			b1_sectors = 8;
			bank1start = bank->base;
			break;
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		case (32 * 1024):
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			str9x_info->bank1 = 1;
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			b1_sectors = 4;
			bank1start = bank->base;
			break;
		default:
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			LOG_ERROR("BUG: unknown bank->size encountered");
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			exit(-1);
	}
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	num_sectors = b0_sectors + b1_sectors;
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	bank->num_sectors = num_sectors;
	bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
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	str9x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
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	num_sectors = 0;
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	for (i = 0; i < b0_sectors; i++)
	{
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		bank->sectors[num_sectors].offset = offset;
		bank->sectors[num_sectors].size = 0x10000;
		offset += bank->sectors[i].size;
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		bank->sectors[num_sectors].is_erased = -1;
		bank->sectors[num_sectors].is_protected = 1;
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		str9x_info->sector_bits[num_sectors++] = (1 << i);
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	}

	for (i = 0; i < b1_sectors; i++)
	{
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		bank->sectors[num_sectors].offset = offset;
		bank->sectors[num_sectors].size = str9x_info->variant == 0 ? 0x2000 : 0x4000;
		offset += bank->sectors[i].size;
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		bank->sectors[num_sectors].is_erased = -1;
		bank->sectors[num_sectors].is_protected = 1;
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		if (str9x_info->variant)
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			str9x_info->sector_bits[num_sectors++] = (1 << i);
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		else
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			str9x_info->sector_bits[num_sectors++] = (1 << (i + 8));
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	}
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	return ERROR_OK;
}

/* flash bank str9x <base> <size> 0 0 <target#>
 */
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static int str9x_flash_bank_command(struct command_context_s *cmd_ctx,
		char *cmd, char **args, int argc, struct flash_bank_s *bank)
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{
	str9x_flash_bank_t *str9x_info;
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	if (argc < 6)
	{
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		LOG_WARNING("incomplete flash_bank str9x configuration");
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		return ERROR_FLASH_BANK_INVALID;
	}
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	str9x_info = malloc(sizeof(str9x_flash_bank_t));
	bank->driver_priv = str9x_info;
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	str9x_build_block_list(bank);
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	str9x_info->write_algorithm = NULL;
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	return ERROR_OK;
}

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static int str9x_protect_check(struct flash_bank_s *bank)
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{
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	int retval;
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	str9x_flash_bank_t *str9x_info = bank->driver_priv;
	target_t *target = bank->target;
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	int i;
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	uint32_t adr;
	uint32_t status = 0;
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	uint16_t hstatus = 0;
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	if (bank->target->state != TARGET_HALTED)
	{
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		LOG_ERROR("Target not halted");
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		return ERROR_TARGET_NOT_HALTED;
	}

	/* read level one protection */
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	if (str9x_info->variant)
	{
		if (str9x_info->bank1)
		{
			adr = bank1start + 0x18;
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			if ((retval = target_write_u16(target, adr, 0x90)) != ERROR_OK)
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			{
				return retval;
			}
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			if ((retval = target_read_u16(target, adr, &hstatus)) != ERROR_OK)
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			{
				return retval;
			}
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			status = hstatus;
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		}
		else
		{
			adr = bank1start + 0x14;
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			if ((retval = target_write_u16(target, adr, 0x90)) != ERROR_OK)
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			{
				return retval;
			}
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			if ((retval = target_read_u32(target, adr, &status)) != ERROR_OK)
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			{
				return retval;
			}
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		}
	}
	else
	{
		adr = bank1start + 0x10;
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		if ((retval = target_write_u16(target, adr, 0x90)) != ERROR_OK)
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		{
			return retval;
		}
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		if ((retval = target_read_u16(target, adr, &hstatus)) != ERROR_OK)
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		{
			return retval;
		}
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		status = hstatus;
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	}
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	/* read array command */
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	if ((retval = target_write_u16(target, adr, 0xFF)) != ERROR_OK)
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	{
		return retval;
	}
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	for (i = 0; i < bank->num_sectors; i++)
	{
		if (status & str9x_info->sector_bits[i])
			bank->sectors[i].is_protected = 1;
		else
			bank->sectors[i].is_protected = 0;
	}
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	return ERROR_OK;
}

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static int str9x_erase(struct flash_bank_s *bank, int first, int last)
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{
	target_t *target = bank->target;
	int i;
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	uint32_t adr;
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	uint8_t status;
	uint8_t erase_cmd;
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	if (bank->target->state != TARGET_HALTED)
	{
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		LOG_ERROR("Target not halted");
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		return ERROR_TARGET_NOT_HALTED;
	}

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	/* Check if we erase whole bank */
	if ((first == 0) && (last == (bank->num_sectors - 1)))
	{
		/* Optimize to run erase bank command instead of sector */
		erase_cmd = 0x80;
	}
	else
	{
		/* Erase sector command */
		erase_cmd = 0x20;
	}
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	for (i = first; i <= last; i++)
	{
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		int retval;
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		adr = bank->base + bank->sectors[i].offset;
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		/* erase sectors */
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		if ((retval = target_write_u16(target, adr, erase_cmd)) != ERROR_OK)
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		{
			return retval;
		}
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		if ((retval = target_write_u16(target, adr, 0xD0)) != ERROR_OK)
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		{
			return retval;
		}
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		/* get status */
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		if ((retval = target_write_u16(target, adr, 0x70)) != ERROR_OK)
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		{
			return retval;
		}
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		int timeout;
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		for (timeout = 0; timeout<1000; timeout++) {
			if ((retval = target_read_u8(target, adr, &status)) != ERROR_OK)
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			{
				return retval;
			}
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			if ( status & 0x80 )
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				break;
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			alive_sleep(1);
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		}
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		if (timeout == 1000)
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		{
			LOG_ERROR("erase timed out");
			return ERROR_FAIL;
		}
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		/* clear status, also clear read array */
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		if ((retval = target_write_u16(target, adr, 0x50)) != ERROR_OK)
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		{
			return retval;
		}
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		/* read array command */
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		if ((retval = target_write_u16(target, adr, 0xFF)) != ERROR_OK)
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		{
			return retval;
		}
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		if ( status & 0x22 )
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		{
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			LOG_ERROR("error erasing flash bank, status: 0x%x", status);
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			return ERROR_FLASH_OPERATION_FAILED;
		}
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		/* If we ran erase bank command, we are finished */
		if (erase_cmd == 0x80)
			break;
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	}
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	for (i = first; i <= last; i++)
		bank->sectors[i].is_erased = 1;

	return ERROR_OK;
}

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static int str9x_protect(struct flash_bank_s *bank,
		int set, int first, int last)
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{
	target_t *target = bank->target;
	int i;
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	uint32_t adr;
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	uint8_t status;
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	if (bank->target->state != TARGET_HALTED)
	{
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		LOG_ERROR("Target not halted");
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		return ERROR_TARGET_NOT_HALTED;
	}
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	for (i = first; i <= last; i++)
	{
		/* Level One Protection */
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		adr = bank->base + bank->sectors[i].offset;
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		target_write_u16(target, adr, 0x60);
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		if ( set )
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			target_write_u16(target, adr, 0x01);
		else
			target_write_u16(target, adr, 0xD0);
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		/* query status */
		target_read_u8(target, adr, &status);
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		/* clear status, also clear read array */
		target_write_u16(target, adr, 0x50);
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		/* read array command */
		target_write_u16(target, adr, 0xFF);
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	}
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	return ERROR_OK;
}

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static int str9x_write_block(struct flash_bank_s *bank,
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		uint8_t *buffer, uint32_t offset, uint32_t count)
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{
	str9x_flash_bank_t *str9x_info = bank->driver_priv;
	target_t *target = bank->target;
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	uint32_t buffer_size = 8192;
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	working_area_t *source;
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	uint32_t address = bank->base + offset;
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	reg_param_t reg_params[4];
	armv4_5_algorithm_t armv4_5_info;
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	int retval = ERROR_OK;
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	uint32_t str9x_flash_write_code[] = {
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					/* write:				*/
		0xe3c14003,	/*	bic	r4, r1, #3		*/
		0xe3a03040,	/*	mov	r3, #0x40		*/
		0xe1c430b0,	/*	strh r3, [r4, #0]	*/
		0xe0d030b2,	/*	ldrh r3, [r0], #2	*/
		0xe0c130b2,	/*	strh r3, [r1], #2	*/
		0xe3a03070,	/*	mov r3, #0x70		*/
		0xe1c430b0,	/*	strh r3, [r4, #0]	*/
					/* busy:				*/
		0xe5d43000,	/*	ldrb r3, [r4, #0]	*/
		0xe3130080,	/*	tst r3, #0x80		*/
		0x0afffffc,	/*	beq busy			*/
		0xe3a05050,	/*	mov	r5, #0x50		*/
		0xe1c450b0,	/*	strh r5, [r4, #0]	*/
		0xe3a050ff,	/*	mov	r5, #0xFF		*/
		0xe1c450b0,	/*	strh r5, [r4, #0]	*/
		0xe3130012,	/*	tst	r3, #0x12		*/
		0x1a000001,	/*	bne exit			*/
		0xe2522001,	/*	subs r2, r2, #1		*/
		0x1affffed,	/*	bne write			*/
					/* exit:				*/
		0xeafffffe,	/*	b exit				*/
	};
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	/* flash write code */
	if (target_alloc_working_area(target, 4 * 19, &str9x_info->write_algorithm) != ERROR_OK)
	{
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		LOG_WARNING("no working area available, can't do block memory writes");
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		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	};
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	target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (uint8_t*)str9x_flash_write_code);
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	/* memory buffer */
	while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
	{
		buffer_size /= 2;
		if (buffer_size <= 256)
		{
			/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
			if (str9x_info->write_algorithm)
				target_free_working_area(target, str9x_info->write_algorithm);
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			LOG_WARNING("no large enough working area available, can't do block memory writes");
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			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
		}
	}
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	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
	armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
	armv4_5_info.core_state = ARMV4_5_STATE_ARM;
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	init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
	init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
	init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
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	while (count > 0)
	{
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		uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
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		target_write_buffer(target, source->address, thisrun_count * 2, buffer);
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		buf_set_u32(reg_params[0].value, 0, 32, source->address);
		buf_set_u32(reg_params[1].value, 0, 32, address);
		buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);

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		if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, str9x_info->write_algorithm->address + (18 * 4), 10000, &armv4_5_info)) != ERROR_OK)
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		{
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			LOG_ERROR("error executing str9x flash write algorithm");
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			retval = ERROR_FLASH_OPERATION_FAILED;
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			break;
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		}
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		if (buf_get_u32(reg_params[3].value, 0, 32) != 0x80)
		{
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			retval = ERROR_FLASH_OPERATION_FAILED;
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			break;
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		}
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		buffer += thisrun_count * 2;
		address += thisrun_count * 2;
		count -= thisrun_count;
	}
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	target_free_working_area(target, source);
	target_free_working_area(target, str9x_info->write_algorithm);
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	destroy_reg_param(&reg_params[0]);
	destroy_reg_param(&reg_params[1]);
	destroy_reg_param(&reg_params[2]);
	destroy_reg_param(&reg_params[3]);
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	return retval;
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}

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static int str9x_write(struct flash_bank_s *bank,
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		uint8_t *buffer, uint32_t offset, uint32_t count)
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{
	target_t *target = bank->target;
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	uint32_t words_remaining = (count / 2);
	uint32_t bytes_remaining = (count & 0x00000001);
	uint32_t address = bank->base + offset;
	uint32_t bytes_written = 0;
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	uint8_t status;
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	int retval;
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	uint32_t check_address = offset;
	uint32_t bank_adr;
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	int i;
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	if (bank->target->state != TARGET_HALTED)
	{
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		LOG_ERROR("Target not halted");
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		return ERROR_TARGET_NOT_HALTED;
	}

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	if (offset & 0x1)
	{
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		LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
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		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
	}
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	for (i = 0; i < bank->num_sectors; i++)
	{
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		uint32_t sec_start = bank->sectors[i].offset;
		uint32_t sec_end = sec_start + bank->sectors[i].size;
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		/* check if destination falls within the current sector */
		if ((check_address >= sec_start) && (check_address < sec_end))
		{
			/* check if destination ends in the current sector */
			if (offset + count < sec_end)
				check_address = offset + count;
			else
				check_address = sec_end;
		}
	}
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	if (check_address != offset + count)
		return ERROR_FLASH_DST_OUT_OF_BANK;
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	/* multiple half words (2-byte) to be programmed? */
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	if (words_remaining > 0)
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	{
		/* try using a block write */
		if ((retval = str9x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
		{
			if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
			{
				/* if block write failed (no sufficient working area),
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				 * we use normal (slow) single dword accesses */
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				LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
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			}
			else if (retval == ERROR_FLASH_OPERATION_FAILED)
			{
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				LOG_ERROR("flash writing failed with error code: 0x%x", retval);
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				return ERROR_FLASH_OPERATION_FAILED;
			}
		}
		else
		{
			buffer += words_remaining * 2;
			address += words_remaining * 2;
			words_remaining = 0;
		}
	}

	while (words_remaining > 0)
	{
		bank_adr = address & ~0x03;
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		/* write data command */
		target_write_u16(target, bank_adr, 0x40);
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		target_write_memory(target, address, 2, 1, buffer + bytes_written);
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		/* get status command */
		target_write_u16(target, bank_adr, 0x70);
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		int timeout;
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		for (timeout = 0; timeout<1000; timeout++)
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		{
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			target_read_u8(target, bank_adr, &status);
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			if ( status & 0x80 )
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				break;
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			alive_sleep(1);
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		}
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		if (timeout == 1000)
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		{
			LOG_ERROR("write timed out");
			return ERROR_FAIL;
		}
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		/* clear status reg and read array */
		target_write_u16(target, bank_adr, 0x50);
		target_write_u16(target, bank_adr, 0xFF);
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		if (status & 0x10)
			return ERROR_FLASH_OPERATION_FAILED;
		else if (status & 0x02)
			return ERROR_FLASH_OPERATION_FAILED;

		bytes_written += 2;
		words_remaining--;
		address += 2;
	}
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	if (bytes_remaining)
	{
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		uint8_t last_halfword[2] = {0xff, 0xff};
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		int i = 0;
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		while (bytes_remaining > 0)
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		{
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			last_halfword[i++] = *(buffer + bytes_written);
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			bytes_remaining--;
			bytes_written++;
		}
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		bank_adr = address & ~0x03;
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		/* write data command */
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		target_write_u16(target, bank_adr, 0x40);
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		target_write_memory(target, address, 2, 1, last_halfword);
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		/* query status command */
		target_write_u16(target, bank_adr, 0x70);
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		int timeout;
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		for (timeout = 0; timeout<1000; timeout++)
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		{
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			target_read_u8(target, bank_adr, &status);
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			if ( status & 0x80 )
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				break;
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			alive_sleep(1);
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		}
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		if (timeout == 1000)
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		{
			LOG_ERROR("write timed out");
			return ERROR_FAIL;
		}
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		/* clear status reg and read array */
		target_write_u16(target, bank_adr, 0x50);
		target_write_u16(target, bank_adr, 0xFF);
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		if (status & 0x10)
			return ERROR_FLASH_OPERATION_FAILED;
		else if (status & 0x02)
			return ERROR_FLASH_OPERATION_FAILED;
	}
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	return ERROR_OK;
}

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static int str9x_probe(struct flash_bank_s *bank)
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{
	return ERROR_OK;
}

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#if 0
static int str9x_handle_part_id_command(struct command_context_s *cmd_ctx,
		char *cmd, char **args, int argc)
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{
	return ERROR_OK;
}
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#endif
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static int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size)
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{
	snprintf(buf, buf_size, "str9x flash driver info" );
	return ERROR_OK;
}

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static int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx,
		char *cmd, char **args, int argc)
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{
	str9x_flash_bank_t *str9x_info;
	flash_bank_t *bank;
	target_t *target = NULL;
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	if (argc < 5)
	{
		return ERROR_COMMAND_SYNTAX_ERROR;
	}
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	bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
	if (!bank)
	{
		command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
		return ERROR_OK;
	}
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	str9x_info = bank->driver_priv;
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	target = bank->target;
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	if (bank->target->state != TARGET_HALTED)
	{
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		LOG_ERROR("Target not halted");
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		return ERROR_TARGET_NOT_HALTED;
	}
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	/* config flash controller */
	target_write_u32(target, FLASH_BBSR, strtoul(args[1], NULL, 0));
	target_write_u32(target, FLASH_NBBSR, strtoul(args[2], NULL, 0));
	target_write_u32(target, FLASH_BBADR, (strtoul(args[3], NULL, 0) >> 2));
	target_write_u32(target, FLASH_NBBADR, (strtoul(args[4], NULL, 0) >> 2));

	/* set bit 18 instruction TCM order as per flash programming manual */
	arm966e_write_cp15(target, 62, 0x40000);
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	/* enable flash bank 1 */
	target_write_u32(target, FLASH_CR, 0x18);
	return ERROR_OK;
}