etb.c 19.1 KB
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/***************************************************************************
 *   Copyright (C) 2007 by Dominic Rath                                    *
 *   Dominic.Rath@gmx.de                                                   *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
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 *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
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 ***************************************************************************/
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#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

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#include "arm.h"
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#include "etm.h"
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#include "etb.h"
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#include "register.h"
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static const char * const etb_reg_list[] = {
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	"ETB_identification",
	"ETB_ram_depth",
	"ETB_ram_width",
	"ETB_status",
	"ETB_ram_data",
	"ETB_ram_read_pointer",
	"ETB_ram_write_pointer",
	"ETB_trigger_counter",
	"ETB_control",
};

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static int etb_get_reg(struct reg *reg);
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static int etb_set_instr(struct etb *etb, uint32_t new_instr)
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{
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	struct jtag_tap *tap;
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	tap = etb->tap;
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	if (tap == NULL)
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		return ERROR_FAIL;
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	if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
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		struct scan_field field;
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		field.num_bits = tap->ir_length;
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		void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
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		field.out_value = t;
		buf_set_u32(t, 0, field.num_bits, new_instr);
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		field.in_value = NULL;
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		jtag_add_ir_scan(tap, &field, TAP_IDLE);
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		free(t);
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	}
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	return ERROR_OK;
}

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static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
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{
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	if (etb->cur_scan_chain != new_scan_chain) {
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		struct scan_field field;
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		field.num_bits = 5;
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		void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
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		field.out_value = t;
		buf_set_u32(t, 0, field.num_bits, new_scan_chain);
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		field.in_value = NULL;
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		/* select INTEST instruction */
		etb_set_instr(etb, 0x2);
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		jtag_add_dr_scan(etb->tap, 1, &field, TAP_IDLE);
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		etb->cur_scan_chain = new_scan_chain;
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		free(t);
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	}

	return ERROR_OK;
}

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static int etb_read_reg_w_check(struct reg *, uint8_t *, uint8_t *);
static int etb_set_reg_w_exec(struct reg *, uint8_t *);
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static int etb_read_reg(struct reg *reg)
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{
	return etb_read_reg_w_check(reg, NULL, NULL);
}

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static int etb_get_reg(struct reg *reg)
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{
	int retval;

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	retval = etb_read_reg(reg);
	if (retval != ERROR_OK) {
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		LOG_ERROR("BUG: error scheduling ETB register read");
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		return retval;
	}

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	retval = jtag_execute_queue();
	if (retval != ERROR_OK) {
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		LOG_ERROR("ETB register read failed");
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		return retval;
	}

	return ERROR_OK;
}

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static const struct reg_arch_type etb_reg_type = {
	.get = etb_get_reg,
	.set = etb_set_reg_w_exec,
};

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struct reg_cache *etb_build_reg_cache(struct etb *etb)
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{
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	struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
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	struct reg *reg_list = NULL;
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	struct etb_reg *arch_info = NULL;
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	int num_regs = 9;
	int i;
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	/* the actual registers are kept in two arrays */
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	reg_list = calloc(num_regs, sizeof(struct reg));
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	arch_info = calloc(num_regs, sizeof(struct etb_reg));
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	/* fill in values for the reg cache */
	reg_cache->name = "etb registers";
	reg_cache->next = NULL;
	reg_cache->reg_list = reg_list;
	reg_cache->num_regs = num_regs;
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	/* set up registers */
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	for (i = 0; i < num_regs; i++) {
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		reg_list[i].name = etb_reg_list[i];
		reg_list[i].size = 32;
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		reg_list[i].dirty = false;
		reg_list[i].valid = false;
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		reg_list[i].value = calloc(1, 4);
		reg_list[i].arch_info = &arch_info[i];
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		reg_list[i].type = &etb_reg_type;
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		reg_list[i].size = 32;
		arch_info[i].addr = i;
		arch_info[i].etb = etb;
	}
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	return reg_cache;
}

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static void etb_getbuf(jtag_callback_data_t arg)
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{
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	uint8_t *in = (uint8_t *)arg;

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	*((uint32_t *)arg) = buf_get_u32(in, 0, 32);
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}

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static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
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{
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	struct scan_field fields[3];
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	int i;
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	etb_scann(etb, 0x0);
	etb_set_instr(etb, 0xc);
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	fields[0].num_bits = 32;
	fields[0].out_value = NULL;
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	fields[0].in_value = NULL;
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	fields[1].num_bits = 7;
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	uint8_t temp1;
	fields[1].out_value = &temp1;
	buf_set_u32(&temp1, 0, 7, 4);
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	fields[1].in_value = NULL;

	fields[2].num_bits = 1;
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	uint8_t temp2;
	fields[2].out_value = &temp2;
	buf_set_u32(&temp2, 0, 1, 0);
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	fields[2].in_value = NULL;
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	jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
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	for (i = 0; i < num_frames; i++) {
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		/* ensure nR/W remains set to read */
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		buf_set_u32(&temp2, 0, 1, 0);
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		/* address remains set to 0x4 (RAM data) until we read the last frame */
		if (i < num_frames - 1)
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			buf_set_u32(&temp1, 0, 7, 4);
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		else
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			buf_set_u32(&temp1, 0, 7, 0);
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		fields[0].in_value = (uint8_t *)(data + i);
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		jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
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		jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
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	}
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	jtag_execute_queue();
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	return ERROR_OK;
}

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static int etb_read_reg_w_check(struct reg *reg,
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	uint8_t *check_value, uint8_t *check_mask)
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{
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	struct etb_reg *etb_reg = reg->arch_info;
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	uint8_t reg_addr = etb_reg->addr & 0x7f;
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	struct scan_field fields[3];
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	LOG_DEBUG("%i", (int)(etb_reg->addr));
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	etb_scann(etb_reg->etb, 0x0);
	etb_set_instr(etb_reg->etb, 0xc);
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	fields[0].num_bits = 32;
	fields[0].out_value = reg->value;
	fields[0].in_value = NULL;
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	fields[0].check_value = NULL;
	fields[0].check_mask = NULL;
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	fields[1].num_bits = 7;
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	uint8_t temp1;
	fields[1].out_value = &temp1;
	buf_set_u32(&temp1, 0, 7, reg_addr);
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	fields[1].in_value = NULL;
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	fields[1].check_value = NULL;
	fields[1].check_mask = NULL;
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	fields[2].num_bits = 1;
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	uint8_t temp2;
	fields[2].out_value = &temp2;
	buf_set_u32(&temp2, 0, 1, 0);
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	fields[2].in_value = NULL;
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	fields[2].check_value = NULL;
	fields[2].check_mask = NULL;
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	jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE);
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	/* read the identification register in the second run, to make sure we
	 * don't read the ETB data register twice, skipping every second entry
	 */
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	buf_set_u32(&temp1, 0, 7, 0x0);
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	fields[0].in_value = reg->value;
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	fields[0].check_value = check_value;
	fields[0].check_mask = check_mask;
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	jtag_add_dr_scan_check(etb_reg->etb->tap, 3, fields, TAP_IDLE);
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	return ERROR_OK;
}

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static int etb_write_reg(struct reg *, uint32_t);
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static int etb_set_reg(struct reg *reg, uint32_t value)
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{
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	int retval;
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	retval = etb_write_reg(reg, value);
	if (retval != ERROR_OK) {
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		LOG_ERROR("BUG: error scheduling ETB register write");
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		return retval;
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	}
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	buf_set_u32(reg->value, 0, reg->size, value);
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	reg->valid = true;
	reg->dirty = false;
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	return ERROR_OK;
}

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static int etb_set_reg_w_exec(struct reg *reg, uint8_t *buf)
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{
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	int retval;
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	etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
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	retval = jtag_execute_queue();
	if (retval != ERROR_OK) {
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		LOG_ERROR("ETB: register write failed");
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		return retval;
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	}
	return ERROR_OK;
}

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static int etb_write_reg(struct reg *reg, uint32_t value)
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{
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	struct etb_reg *etb_reg = reg->arch_info;
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	uint8_t reg_addr = etb_reg->addr & 0x7f;
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	struct scan_field fields[3];
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	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
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	etb_scann(etb_reg->etb, 0x0);
	etb_set_instr(etb_reg->etb, 0xc);
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	fields[0].num_bits = 32;
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	uint8_t temp0[4];
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	fields[0].out_value = temp0;
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	buf_set_u32(temp0, 0, 32, value);
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	fields[0].in_value = NULL;
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	fields[1].num_bits = 7;
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	uint8_t temp1;
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	fields[1].out_value = &temp1;
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	buf_set_u32(&temp1, 0, 7, reg_addr);
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	fields[1].in_value = NULL;
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	fields[2].num_bits = 1;
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	uint8_t temp2;
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	fields[2].out_value = &temp2;
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	buf_set_u32(&temp2, 0, 1, 1);
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	fields[2].in_value = NULL;

	jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE);
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	return ERROR_OK;
}

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COMMAND_HANDLER(handle_etb_config_command)
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{
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	struct target *target;
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	struct jtag_tap *tap;
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	struct arm *arm;
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	if (CMD_ARGC != 2)
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		return ERROR_COMMAND_SYNTAX_ERROR;

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	target = get_target(CMD_ARGV[0]);
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	if (!target) {
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		LOG_ERROR("ETB: target '%s' not defined", CMD_ARGV[0]);
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		return ERROR_FAIL;
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	}
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	arm = target_to_arm(target);
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	if (!is_arm(arm)) {
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		command_print(CMD_CTX, "ETB: '%s' isn't an ARM", CMD_ARGV[0]);
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		return ERROR_FAIL;
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	}
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	tap = jtag_tap_by_string(CMD_ARGV[1]);
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	if (tap == NULL) {
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		command_print(CMD_CTX, "ETB: TAP %s does not exist", CMD_ARGV[1]);
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		return ERROR_FAIL;
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	}
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	if (arm->etm) {
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		struct etb *etb = malloc(sizeof(struct etb));
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		arm->etm->capture_driver_priv = etb;
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		etb->tap  = tap;
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		etb->cur_scan_chain = 0xffffffff;
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		etb->reg_cache = NULL;
		etb->ram_width = 0;
		etb->ram_depth = 0;
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	} else {
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		LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured");
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		return ERROR_FAIL;
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	}

	return ERROR_OK;
}

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COMMAND_HANDLER(handle_etb_trigger_percent_command)
{
	struct target *target;
	struct arm *arm;
	struct etm_context *etm;
	struct etb *etb;

	target = get_current_target(CMD_CTX);
	arm = target_to_arm(target);
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	if (!is_arm(arm)) {
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		command_print(CMD_CTX, "ETB: current target isn't an ARM");
		return ERROR_FAIL;
	}

	etm = arm->etm;
	if (!etm) {
		command_print(CMD_CTX, "ETB: target has no ETM configured");
		return ERROR_FAIL;
	}
	if (etm->capture_driver != &etb_capture_driver) {
		command_print(CMD_CTX, "ETB: target not using ETB");
		return ERROR_FAIL;
	}
	etb = arm->etm->capture_driver_priv;

	if (CMD_ARGC > 0) {
		uint32_t new_value;

		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
		if ((new_value < 2) || (new_value > 100))
			command_print(CMD_CTX,
				"valid percentages are 2%% to 100%%");
		else
			etb->trigger_percent = (unsigned) new_value;
	}

	command_print(CMD_CTX, "%d percent of tracebuffer fills after trigger",
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		etb->trigger_percent);
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	return ERROR_OK;
}

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static const struct command_registration etb_config_command_handlers[] = {
	{
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		/* NOTE:  with ADIv5, ETBs are accessed using DAP operations,
		 * possibly over SWD, not through separate TAPs...
		 */
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		.name = "config",
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		.handler = handle_etb_config_command,
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		.mode = COMMAND_CONFIG,
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		.help = "Associate ETB with target and JTAG TAP.",
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		.usage = "target tap",
	},
	{
		.name = "trigger_percent",
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		.handler = handle_etb_trigger_percent_command,
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		.mode = COMMAND_EXEC,
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		.help = "Set percent of trace buffer to be filled "
			"after the trigger occurs (2..100).",
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		.usage = "[percent]",
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	},
	COMMAND_REGISTRATION_DONE
};
static const struct command_registration etb_command_handlers[] = {
	{
		.name = "etb",
		.mode = COMMAND_ANY,
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		.help = "Embedded Trace Buffer command group",
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		.chain = etb_config_command_handlers,
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		.usage = "",
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	},
	COMMAND_REGISTRATION_DONE
};

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static int etb_init(struct etm_context *etm_ctx)
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{
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	struct etb *etb = etm_ctx->capture_driver_priv;
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	etb->etm_ctx = etm_ctx;
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	/* identify ETB RAM depth and width */
	etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
	etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
	jtag_execute_queue();

	etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
	etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
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	etb->trigger_percent = 50;

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	return ERROR_OK;
}

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static trace_status_t etb_status(struct etm_context *etm_ctx)
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{
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	struct etb *etb = etm_ctx->capture_driver_priv;
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	struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL];
	struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS];
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	trace_status_t retval = 0;
	int etb_timeout = 100;
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	etb->etm_ctx = etm_ctx;
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	/* read control and status registers */
	etb_read_reg(control);
	etb_read_reg(status);
	jtag_execute_queue();
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	/* See if it's (still) active */
	retval = buf_get_u32(control->value, 0, 1) ? TRACE_RUNNING : TRACE_IDLE;
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	/* check Full bit to identify wraparound/overflow */
	if (buf_get_u32(status->value, 0, 1) == 1)
		retval |= TRACE_OVERFLOWED;
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	/* check Triggered bit to identify trigger condition */
	if (buf_get_u32(status->value, 1, 1) == 1)
		retval |= TRACE_TRIGGERED;
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	/* check AcqComp to see if trigger counter dropped to zero */
	if (buf_get_u32(status->value, 2, 1) == 1) {
		/* wait for DFEmpty */
		while (etb_timeout-- && buf_get_u32(status->value, 3, 1) == 0)
			etb_get_reg(status);
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		if (etb_timeout == 0)
			LOG_ERROR("ETB:  DFEmpty won't go high, status 0x%02x",
				(unsigned) buf_get_u32(status->value, 0, 4));
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		if (!(etm_ctx->capture_status & TRACE_TRIGGERED))
			LOG_WARNING("ETB: trace complete without triggering?");
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		retval |= TRACE_COMPLETED;
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	}
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	/* NOTE: using a trigger is optional; and at least ETB11 has a mode
	 * where it can ignore the trigger counter.
	 */

	/* update recorded state */
	etm_ctx->capture_status = retval;

	return retval;
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}

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static int etb_read_trace(struct etm_context *etm_ctx)
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{
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	struct etb *etb = etm_ctx->capture_driver_priv;
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	int first_frame = 0;
	int num_frames = etb->ram_depth;
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	uint32_t *trace_data = NULL;
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	int i, j;
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	etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
	etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
	jtag_execute_queue();
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	/* check if we overflowed, and adjust first frame of the trace accordingly
	 * if we didn't overflow, read only up to the frame that would be written next,
	 * i.e. don't read invalid entries
	 */
	if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
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		first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value,
				0,
				32);
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	else
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		num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value,
				0,
				32);
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	etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);

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	/* read data into temporary array for unpacking */
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	trace_data = malloc(sizeof(uint32_t) * num_frames);
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	etb_read_ram(etb, trace_data, num_frames);

	if (etm_ctx->trace_depth > 0)
		free(etm_ctx->trace_data);
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	if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
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		etm_ctx->trace_depth = num_frames * 3;
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	else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
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		etm_ctx->trace_depth = num_frames * 2;
	else
		etm_ctx->trace_depth = num_frames;

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	etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
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	for (i = 0, j = 0; i < num_frames; i++) {
		if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT) {
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			/* trace word j */
			etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
			etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
			etm_ctx->trace_data[j].flags = 0;
			if ((trace_data[i] & 0x80) >> 7)
				etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
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			if (etm_ctx->trace_data[j].pipestat == STAT_TR) {
				etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet &
					0x7;
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				etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
			}
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			/* trace word j + 1 */
			etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
			etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
			etm_ctx->trace_data[j + 1].flags = 0;
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			if ((trace_data[i] & 0x8000) >> 15)
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				etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
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			if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR) {
				etm_ctx->trace_data[j +
				1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
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				etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
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			}
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			/* trace word j + 2 */
			etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
			etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
			etm_ctx->trace_data[j + 2].flags = 0;
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			if ((trace_data[i] & 0x800000) >> 23)
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				etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
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			if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR) {
				etm_ctx->trace_data[j +
				2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
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				etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
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			}
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			j += 3;
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		} else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) {
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			/* trace word j */
			etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
			etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
			etm_ctx->trace_data[j].flags = 0;
			if ((trace_data[i] & 0x800) >> 11)
				etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
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			if (etm_ctx->trace_data[j].pipestat == STAT_TR) {
				etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet &
					0x7;
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				etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
			}

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			/* trace word j + 1 */
			etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
			etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
			etm_ctx->trace_data[j + 1].flags = 0;
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			if ((trace_data[i] & 0x800000) >> 23)
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				etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
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			if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR) {
				etm_ctx->trace_data[j +
				1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
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				etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
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			}
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			j += 2;
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		} else {
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			/* trace word j */
			etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
			etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
			etm_ctx->trace_data[j].flags = 0;
			if ((trace_data[i] & 0x80000) >> 19)
				etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
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			if (etm_ctx->trace_data[j].pipestat == STAT_TR) {
				etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet &
					0x7;
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				etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
			}
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			j += 1;
		}
	}
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	free(trace_data);
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	return ERROR_OK;
}

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static int etb_start_capture(struct etm_context *etm_ctx)
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{
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	struct etb *etb = etm_ctx->capture_driver_priv;
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	uint32_t etb_ctrl_value = 0x1;
	uint32_t trigger_count;
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	if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED) {
		if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT) {
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			LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
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			return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
		}
		etb_ctrl_value |= 0x2;
	}
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	if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
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		LOG_ERROR("ETB: can't run in multiplexed mode");
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		return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
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	}
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	trigger_count = (etb->ram_depth * etb->trigger_percent) / 100;
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	etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
	etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
	etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
	jtag_execute_queue();
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	/* we're starting a new trace, initialize capture status */
	etm_ctx->capture_status = TRACE_RUNNING;
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	return ERROR_OK;
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}

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static int etb_stop_capture(struct etm_context *etm_ctx)
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{
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	struct etb *etb = etm_ctx->capture_driver_priv;
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	struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
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	etb_write_reg(etb_ctrl_reg, 0x0);
	jtag_execute_queue();
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	/* trace stopped, just clear running flag, but preserve others */
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	etm_ctx->capture_status &= ~TRACE_RUNNING;
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	return ERROR_OK;
}

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struct etm_capture_driver etb_capture_driver = {
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	.name = "etb",
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	.commands = etb_command_handlers,
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	.init = etb_init,
	.status = etb_status,
	.start_capture = etb_start_capture,
	.stop_capture = etb_stop_capture,
	.read_trace = etb_read_trace,
};