armv4_5.h 11.6 KB
Newer Older
1
2
3
4
/***************************************************************************
 *   Copyright (C) 2005 by Dominic Rath                                    *
 *   Dominic.Rath@gmx.de                                                   *
 *                                                                         *
5
6
7
 *   Copyright (C) 2008 by Spencer Oliver                                  *
 *   spen@spen-soft.co.uk                                                  *
 *                                                                         *
8
9
10
 *   Copyright (C) 2009 by Øyvind Harboe                                   *
 *   oyvind.harboe@zylin.com                                               *
 *                                                                         *
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 ***************************************************************************/
#ifndef ARMV4_5_H
#define ARMV4_5_H

#include "register.h"
#include "target.h"
31
#include "log.h"
32
#include "etm.h"
33

34
typedef enum armv4_5_mode
35
{
36
37
38
39
	ARMV4_5_MODE_USR = 16,
	ARMV4_5_MODE_FIQ = 17,
	ARMV4_5_MODE_IRQ = 18,
	ARMV4_5_MODE_SVC = 19,
40
41
42
43
	ARMV4_5_MODE_ABT = 23,
	ARMV4_5_MODE_UND = 27,
	ARMV4_5_MODE_SYS = 31,
	ARMV4_5_MODE_ANY = -1
44
} armv4_5_mode_t;
45

46
extern char** armv4_5_mode_strings;
47

48
typedef enum armv4_5_state
49
50
51
52
{
	ARMV4_5_STATE_ARM,
	ARMV4_5_STATE_THUMB,
	ARMV4_5_STATE_JAZELLE,
53
} armv4_5_state_t;
54
55
56
57
58
59
60
61
62
63
64

extern char* armv4_5_state_strings[];

extern int armv4_5_core_reg_map[7][17];

#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
		cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
		cache->reg_list[armv4_5_core_reg_map[mode][num]]

/* offsets into armv4_5 core register cache */
65
enum
66
67
68
69
70
71
72
73
74
75
76
{
	ARMV4_5_CPSR = 31,
	ARMV4_5_SPSR_FIQ = 32,
	ARMV4_5_SPSR_IRQ = 33,
	ARMV4_5_SPSR_SVC = 34,
	ARMV4_5_SPSR_ABT = 35,
	ARMV4_5_SPSR_UND = 36
};

#define ARMV4_5_COMMON_MAGIC 0x0A450A45

77
78
79
80
81
82
83
84
85
86
87
/* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
#define armv4_5_common_s arm

/**
 * Represents a generic ARM core, with standard application registers.
 *
 * There are sixteen application registers (including PC, SP, LR) and a PSR.
 * Cortex-M series cores do not support as many core states or shadowed
 * registers as traditional ARM cores, and only support Thumb2 instructions.
 */
typedef struct arm
88
89
90
{
	int common_magic;
	reg_cache_t *core_cache;
91

David Brownell's avatar
David Brownell committed
92
	int /* armv4_5_mode */ core_mode;
93
	enum armv4_5_state core_state;
94
95

	/** Flag reporting unavailability of the BKPT instruction. */
96
	bool is_armv4;
97
98
99
100

	/** Handle for the Embedded Trace Module, if one is present. */
	struct etm *etm;

101
	int (*full_context)(struct target_s *target);
102
103
104
105
	int (*read_core_reg)(struct target_s *target,
			int num, enum armv4_5_mode mode);
	int (*write_core_reg)(struct target_s *target,
			int num, enum armv4_5_mode mode, uint32_t value);
106
107
108
	void *arch_info;
} armv4_5_common_t;

109
110
111
112
#define target_to_armv4_5 target_to_arm

/** Convert target handle to generic ARM target state handle. */
static inline struct arm *target_to_arm(struct target_s *target)
113
114
115
116
{
	return target->arch_info;
}

117
118
119
120
121
static inline bool is_arm(struct arm *arm)
{
	return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
}

122
123
124
typedef struct armv4_5_algorithm_s
{
	int common_magic;
125

126
127
128
129
130
131
132
133
134
135
136
137
	enum armv4_5_mode core_mode;
	enum armv4_5_state core_state;
} armv4_5_algorithm_t;

typedef struct armv4_5_core_reg_s
{
	int num;
	enum armv4_5_mode mode;
	target_t *target;
	armv4_5_common_t *armv4_5_common;
} armv4_5_core_reg_t;

138
139
reg_cache_t* armv4_5_build_reg_cache(target_t *target,
		armv4_5_common_t *armv4_5_common);
140
141
142
143
144
145
146
147
148
149
150
151
152
153

/* map psr mode bits to linear number */
static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
{
	switch (mode)
	{
		case ARMV4_5_MODE_USR: return 0; break;
		case ARMV4_5_MODE_FIQ: return 1; break;
		case ARMV4_5_MODE_IRQ: return 2; break;
		case ARMV4_5_MODE_SVC: return 3; break;
		case ARMV4_5_MODE_ABT: return 4; break;
		case ARMV4_5_MODE_UND: return 5; break;
		case ARMV4_5_MODE_SYS: return 6; break;
		case ARMV4_5_MODE_ANY: return 0; break;	/* map MODE_ANY to user mode */
154
		default:
155
			LOG_ERROR("invalid mode value encountered %d", mode);
156
157
158
159
160
161
162
			return -1;
	}
}

/* map linear number to mode bits */
static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
{
163
	switch (number)
164
165
166
167
168
169
170
171
	{
		case 0: return ARMV4_5_MODE_USR; break;
		case 1: return ARMV4_5_MODE_FIQ; break;
		case 2: return ARMV4_5_MODE_IRQ; break;
		case 3: return ARMV4_5_MODE_SVC; break;
		case 4: return ARMV4_5_MODE_ABT; break;
		case 5: return ARMV4_5_MODE_UND; break;
		case 6: return ARMV4_5_MODE_SYS; break;
172
		default:
173
			LOG_ERROR("mode index out of bounds %d", number);
174
			return ARMV4_5_MODE_ANY;
175
176
177
	}
};

178
179
180
int armv4_5_arch_state(struct target_s *target);
int armv4_5_get_gdb_reg_list(target_t *target,
		reg_t **reg_list[], int *reg_list_size);
181

182
183
int armv4_5_register_commands(struct command_context_s *cmd_ctx);
int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
184

185
186
187
188
189
int armv4_5_run_algorithm(struct target_s *target,
		int num_mem_params, mem_param_t *mem_params,
		int num_reg_params, reg_param_t *reg_params,
		uint32_t entry_point, uint32_t exit_point,
		int timeout_ms, void *arch_info);
190

191
int armv4_5_invalidate_core_regs(target_t *target);
192
193
194

/* ARM mode instructions
 */
195

196
197
198
199
/* Store multiple increment after
 * Rn: base register
 * List: for each bit in list: store register
 * S: in priviledged mode: store user-mode registers
zwelch's avatar
zwelch committed
200
 * W = 1: update the base register. W = 0: leave the base register untouched
201
 */
202
#define ARMV4_5_STMIA(Rn, List, S, W)	(0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
203
204
205
206
207

/* Load multiple increment after
 * Rn: base register
 * List: for each bit in list: store register
 * S: in priviledged mode: store user-mode registers
zwelch's avatar
zwelch committed
208
 * W = 1: update the base register. W = 0: leave the base register untouched
209
 */
210
#define ARMV4_5_LDMIA(Rn, List, S, W)	(0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
211
212
213
214
215

/* MOV r8, r8 */
#define ARMV4_5_NOP					(0xe1a08008)

/* Move PSR to general purpose register
zwelch's avatar
zwelch committed
216
 * R = 1: SPSR R = 0: CPSR
217
218
 * Rn: target register
 */
219
#define ARMV4_5_MRS(Rn, R)			(0xe10f0000 | ((R) << 22) | ((Rn) << 12))
220
221
222
223
224

/* Store register
 * Rd: register to store
 * Rn: base register
 */
225
#define ARMV4_5_STR(Rd, Rn)			(0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
226
227
228
229
230

/* Load register
 * Rd: register to load
 * Rn: base register
 */
231
#define ARMV4_5_LDR(Rd, Rn)			(0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
232
233

/* Move general purpose register to PSR
zwelch's avatar
zwelch committed
234
 * R = 1: SPSR R = 0: CPSR
235
236
237
238
 * Field: Field mask
 * 1: control field 2: extension field 4: status field 8: flags field
 * Rm: source register
 */
239
240
#define ARMV4_5_MSR_GP(Rm, Field, R)	(0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
#define ARMV4_5_MSR_IM(Im, Rotate, Field, R)	(0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
241
242
243
244
245

/* Load Register Halfword Immediate Post-Index
 * Rd: register to load
 * Rn: base register
 */
246
#define ARMV4_5_LDRH_IP(Rd, Rn)	(0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
247
248
249
250
251

/* Load Register Byte Immediate Post-Index
 * Rd: register to load
 * Rn: base register
 */
252
#define ARMV4_5_LDRB_IP(Rd, Rn)	(0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
253
254
255
256
257

/* Store register Halfword Immediate Post-Index
 * Rd: register to store
 * Rn: base register
 */
258
#define ARMV4_5_STRH_IP(Rd, Rn)	(0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
259
260
261
262
263

/* Store register Byte Immediate Post-Index
 * Rd: register to store
 * Rn: base register
 */
264
#define ARMV4_5_STRB_IP(Rd, Rn)	(0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
265
266
267
268
269

/* Branch (and Link)
 * Im: Branch target (left-shifted by 2 bits, added to PC)
 * L: 1: branch and link 0: branch only
 */
270
#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
271
272
273
274

/* Branch and exchange (ARM state)
 * Rm: register holding branch target address
 */
275
#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
276

277
278
279
280
281
282
283
284
/* Move to ARM register from coprocessor
 * CP: Coprocessor number
 * op1: Coprocessor opcode
 * Rd: destination register
 * CRn: first coprocessor operand
 * CRm: second coprocessor operand
 * op2: Second coprocessor opcode
 */
285
#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
286
287
288
289
290
291
292
293
294

/* Move to coprocessor from ARM register
 * CP: Coprocessor number
 * op1: Coprocessor opcode
 * Rd: destination register
 * CRn: first coprocessor operand
 * CRm: second coprocessor operand
 * op2: Second coprocessor opcode
 */
295
#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
296

drath's avatar
drath committed
297
298
299
300
301
/* Breakpoint instruction (ARMv5)
 * Im: 16-bit immediate
 */
#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))

302

303
304
/* Thumb mode instructions
 */
305

306
307
308
309
/* Store register (Thumb mode)
 * Rd: source register
 * Rn: base register
 */
310
#define ARMV4_5_T_STR(Rd, Rn)	((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
311
312
313
314
315

/* Load register (Thumb state)
 * Rd: destination register
 * Rn: base register
 */
316
#define ARMV4_5_T_LDR(Rd, Rn)	((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
317

318
319
320
321
/* Load multiple (Thumb state)
 * Rn: base register
 * List: for each bit in list: store register
 */
322
#define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
323

324
325
326
/* Load register with PC relative addressing
 * Rd: register to load
 */
327
328
#define ARMV4_5_T_LDR_PCREL(Rd)	((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))

329
330
331
332
/* Move hi register (Thumb mode)
 * Rd: destination register
 * Rm: source register
 */
333
#define ARMV4_5_T_MOV(Rd, Rm)	((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
334
335
336

/* No operation (Thumb mode)
 */
337
#define ARMV4_5_T_NOP	(0x46c0 | (0x46c0 << 16))
338
339
340
341
342

/* Move immediate to register (Thumb state)
 * Rd: destination register
 * Im: 8-bit immediate value
 */
343
#define ARMV4_5_T_MOV_IM(Rd, Im)	((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
344
345
346
347

/* Branch and Exchange
 * Rm: register containing branch target
 */
348
#define ARMV4_5_T_BX(Rm)		((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
349
350
351
352

/* Branch (Thumb state)
 * Imm: Branch target
 */
353
#define ARMV4_5_T_B(Imm)	((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
354

drath's avatar
drath committed
355
356
357
358
359
/* Breakpoint instruction (ARMv5) (Thumb state)
 * Im: 8-bit immediate
 */
#define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))

360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
/* build basic mrc/mcr opcode */

static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
{
	uint32_t t = 0;
	t|=op1<<21;
	t|=op2<<5;
	t|=CRn<<16;
	t|=CRm<<0;
	return t;
}




375
#endif /* ARMV4_5_H */