arm7_9_common.c 80 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
/***************************************************************************
 *   Copyright (C) 2005 by Dominic Rath                                    *
 *   Dominic.Rath@gmx.de                                                   *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 ***************************************************************************/
20
#ifdef HAVE_CONFIG_H
21
#include "config.h"
22
23
24
#endif

#include "replacements.h"
25
26
27

#include "embeddedice.h"
#include "target.h"
28
#include "target_request.h"
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
#include "armv4_5.h"
#include "arm_jtag.h"
#include "jtag.h"
#include "log.h"
#include "arm7_9_common.h"
#include "breakpoints.h"

#include <stdlib.h>
#include <string.h>
#include <unistd.h>

#include <sys/types.h>
#include <sys/stat.h>
#include <sys/time.h>
#include <errno.h>

int arm7_9_debug_entry(target_t *target);
int arm7_9_enable_sw_bkpts(struct target_s *target);

/* command handler forward declarations */
int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56
int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57
int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58
int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89

int arm7_9_reinit_embeddedice(target_t *target)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	
	breakpoint_t *breakpoint = target->breakpoints;
	
	arm7_9->wp_available = 2;
	arm7_9->wp0_used = 0;
	arm7_9->wp1_used = 0;
		
	/* mark all hardware breakpoints as unset */
	while (breakpoint)
	{
		if (breakpoint->type == BKPT_HARD)
		{
			breakpoint->set = 0;
		}
		breakpoint = breakpoint->next;
	}
		
	if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
	{
		arm7_9->sw_bkpts_enabled = 0;
		arm7_9_enable_sw_bkpts(target);
	}
	
	return ERROR_OK;
}

90
91
/* set things up after a reset / on startup */
int arm7_9_setup(target_t *target)
92
{
93
	/* a test-logic reset have occured
94
95
96
	 * the EmbeddedICE registers have been reset
	 * hardware breakpoints have been cleared
	 */
97
	return arm7_9_reinit_embeddedice(target);
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
}

int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	
	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
	{
		return -1;
	}
	
	if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
	{
		return -1;
	}
	
	*armv4_5_p = armv4_5;
	*arm7_9_p = arm7_9;
	
	return ERROR_OK;
}

int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	
	if (target->state != TARGET_HALTED)
	{
128
		LOG_WARNING("target not halted");
129
130
131
132
133
134
135
136
		return ERROR_TARGET_NOT_HALTED;
	}
	
	if (arm7_9->force_hw_bkpts)
		breakpoint->type = BKPT_HARD;

	if (breakpoint->set)
	{
137
		LOG_WARNING("breakpoint already set");
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
		return ERROR_OK;
	}

	if (breakpoint->type == BKPT_HARD)
	{
		/* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
		u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
		if (!arm7_9->wp0_used)
		{
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);

			jtag_execute_queue();
			arm7_9->wp0_used = 1;
			breakpoint->set = 1;
		}
		else if (!arm7_9->wp1_used)
		{
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);

			jtag_execute_queue();
			arm7_9->wp1_used = 1;
			breakpoint->set = 2;
		}
		else
		{
171
			LOG_ERROR("BUG: no hardware comparator available");
172
173
174
175
176
177
178
			return ERROR_OK;
		}
	}
	else if (breakpoint->type == BKPT_SOFT)
	{
		if (breakpoint->length == 4)
		{
ntfreak's avatar
ntfreak committed
179
			u32 verify = 0xffffffff;
180
			/* keep the original instruction in target endianness */
181
			target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
drath's avatar
drath committed
182
			/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
183
			target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
ntfreak's avatar
ntfreak committed
184
185
186
187
			
			target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
			if (verify != arm7_9->arm_bkpt)
			{
188
				LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
ntfreak's avatar
ntfreak committed
189
190
				return ERROR_OK;
			}
191
192
193
		}
		else
		{
ntfreak's avatar
ntfreak committed
194
			u16 verify = 0xffff;
195
			/* keep the original instruction in target endianness */
196
			target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
drath's avatar
drath committed
197
198
			/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
			target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
ntfreak's avatar
ntfreak committed
199
200
201
202
			
			target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
			if (verify != arm7_9->thumb_bkpt)
			{
203
				LOG_ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
ntfreak's avatar
ntfreak committed
204
205
				return ERROR_OK;
			}
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
		}
		breakpoint->set = 1;
	}

	return ERROR_OK;

}

int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	
	if (target->state != TARGET_HALTED)
	{
221
		LOG_WARNING("target not halted");
222
223
224
225
226
		return ERROR_TARGET_NOT_HALTED;
	}

	if (!breakpoint->set)
	{
227
		LOG_WARNING("breakpoint not set");
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
		return ERROR_OK;
	}
	
	if (breakpoint->type == BKPT_HARD)
	{
		if (breakpoint->set == 1)
		{
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
			jtag_execute_queue();
			arm7_9->wp0_used = 0;
		}
		else if (breakpoint->set == 2)
		{
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
			jtag_execute_queue();
			arm7_9->wp1_used = 0;
		}
		breakpoint->set = 0;
	}
	else
	{
249
		/* restore original instruction (kept in target endianness) */
250
251
		if (breakpoint->length == 4)
		{
252
253
254
255
256
			u32 current_instr;
			/* check that user program as not modified breakpoint instruction */
			target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
			if (current_instr==arm7_9->arm_bkpt)
				target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
257
258
259
		}
		else
		{
260
261
262
263
264
			u16 current_instr;
			/* check that user program as not modified breakpoint instruction */
			target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
			if (current_instr==arm7_9->thumb_bkpt)
				target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
265
266
267
268
269
270
271
		}
		breakpoint->set = 0;
	}

	return ERROR_OK;
}

272
int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
273
274
275
276
277
278
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	
	if (target->state != TARGET_HALTED)
	{
279
		LOG_WARNING("target not halted");
280
281
282
283
284
		return ERROR_TARGET_NOT_HALTED;
	}
	
	if (arm7_9->force_hw_bkpts)
	{
285
		LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
286
		breakpoint->type = BKPT_HARD;
287
288
	}
	
289
	if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
290
	{
291
		LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
292
293
294
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}
	
295
	if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
296
	{
297
		LOG_INFO("no watchpoint unit available for hardware breakpoint");
298
299
300
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}
	
301
	if ((breakpoint->length != 2) && (breakpoint->length != 4))
302
	{
303
		LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
304
305
306
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}
	
307
	if (breakpoint->type == BKPT_HARD)
308
309
		arm7_9->wp_available--;
	
310
311
312
313
314
315
316
317
318
319
	return ERROR_OK;
}

int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	
	if (target->state != TARGET_HALTED)
	{
320
		LOG_WARNING("target not halted");
321
322
323
324
325
326
327
328
		return ERROR_TARGET_NOT_HALTED;
	}
	
	if (breakpoint->set)
	{
		arm7_9_unset_breakpoint(target, breakpoint);
	}
	
329
330
	if (breakpoint->type == BKPT_HARD)
		arm7_9->wp_available++;
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
	
	return ERROR_OK;
}

int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	int rw_mask = 1;
	u32 mask;
	
	mask = watchpoint->length - 1;
	
	if (target->state != TARGET_HALTED)
	{
346
		LOG_WARNING("target not halted");
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
		return ERROR_TARGET_NOT_HALTED;
	}
	
	if (watchpoint->rw == WPT_ACCESS)
		rw_mask = 0;
	else
		rw_mask = 1;
	
	if (!arm7_9->wp0_used)
	{
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
		if( watchpoint->mask != 0xffffffffu )
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));

		jtag_execute_queue();
		watchpoint->set = 1;
		arm7_9->wp0_used = 2;
	}
	else if (!arm7_9->wp1_used)
	{
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
		if( watchpoint->mask != 0xffffffffu )
			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));

		jtag_execute_queue();
		watchpoint->set = 2;
		arm7_9->wp1_used = 2;
	} 
	else
	{
385
		LOG_ERROR("BUG: no hardware comparator available");
386
387
388
389
390
391
392
393
394
395
396
397
398
		return ERROR_OK;
	}
	
	return ERROR_OK;
}

int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	
	if (target->state != TARGET_HALTED)
	{
399
		LOG_WARNING("target not halted");
400
401
402
403
404
		return ERROR_TARGET_NOT_HALTED;
	}
	
	if (!watchpoint->set)
	{
405
		LOG_WARNING("breakpoint not set");
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
		return ERROR_OK;
	}
	
	if (watchpoint->set == 1)
	{
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
		jtag_execute_queue();
		arm7_9->wp0_used = 0;
	}
	else if (watchpoint->set == 2)
	{
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
		jtag_execute_queue();
		arm7_9->wp1_used = 0;
	}
	watchpoint->set = 0;

	return ERROR_OK;
}

426
int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
427
428
429
430
431
432
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	
	if (target->state != TARGET_HALTED)
	{
433
		LOG_WARNING("target not halted");
434
435
436
437
438
439
440
441
		return ERROR_TARGET_NOT_HALTED;
	}
	
	if (arm7_9->wp_available < 1)
	{
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}
	
442
	if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
	{
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}
	
	arm7_9->wp_available--;
		
	return ERROR_OK;
}

int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	
	if (target->state != TARGET_HALTED)
	{
459
		LOG_WARNING("target not halted");
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
		return ERROR_TARGET_NOT_HALTED;
	}
	
	if (watchpoint->set)
	{
		arm7_9_unset_watchpoint(target, watchpoint);
	}
		
	arm7_9->wp_available++;
	
	return ERROR_OK;
}

int arm7_9_enable_sw_bkpts(struct target_s *target)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	int retval;
	
	if (arm7_9->sw_bkpts_enabled)
		return ERROR_OK;
	
482
	if (arm7_9->wp_available < 1)
483
	{
484
		LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
485
486
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}
487
	arm7_9->wp_available--;
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
	
	if (!arm7_9->wp0_used)
	{
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
		arm7_9->sw_bkpts_enabled = 1;
		arm7_9->wp0_used = 3;
	}
	else if (!arm7_9->wp1_used)
	{
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
		arm7_9->sw_bkpts_enabled = 2;
		arm7_9->wp1_used = 3;
	}
	else
	{
511
		LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
512
		return ERROR_FAIL;
513
514
515
516
	}
	
	if ((retval = jtag_execute_queue()) != ERROR_OK)
	{
517
		LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
518
		return ERROR_FAIL;
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
	};
	
	return ERROR_OK;
}

int arm7_9_disable_sw_bkpts(struct target_s *target)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	
	if (!arm7_9->sw_bkpts_enabled)
		return ERROR_OK;
	
	if (arm7_9->sw_bkpts_enabled == 1)
	{
		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
		arm7_9->sw_bkpts_enabled = 0;
		arm7_9->wp0_used = 0;
		arm7_9->wp_available++;
	}
	else if (arm7_9->sw_bkpts_enabled == 2)
	{
		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
		arm7_9->sw_bkpts_enabled = 0;
		arm7_9->wp1_used = 0;
		arm7_9->wp_available++;
	}

	return ERROR_OK;
}

int arm7_9_execute_sys_speed(struct target_s *target)
{
	int timeout;
	int retval;
	
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
559
				
560
561
	/* set RESTART instruction */
	jtag_add_end_state(TAP_RTI);
oharboe's avatar
oharboe committed
562
563
564
565
	if (arm7_9->need_bypass_before_restart) {
		arm7_9->need_bypass_before_restart = 0;
		arm_jtag_set_instr(jtag_info, 0xf, NULL);
	}
566
	arm_jtag_set_instr(jtag_info, 0x4, NULL);
567
568
569
570
571
572
573
574
575
576
577
578
579
580
	
	for (timeout=0; timeout<50; timeout++)
	{
		/* read debug status register */
		embeddedice_read_reg(dbg_stat);
		if ((retval = jtag_execute_queue()) != ERROR_OK)
			return retval;
		if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
				   && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
			break;
		usleep(100000);	
	}
	if (timeout == 50)
	{
581
		LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
582
583
584
585
586
587
588
589
		return ERROR_TARGET_TIMEOUT;
	}
	
	return ERROR_OK;
}

int arm7_9_execute_fast_sys_speed(struct target_s *target)
{
mifi's avatar
mifi committed
590
591
	static int set=0;
	static u8 check_value[4], check_mask[4];
592
593
594
595
596
	
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
597
				
598
599
	/* set RESTART instruction */
	jtag_add_end_state(TAP_RTI);
oharboe's avatar
oharboe committed
600
601
602
603
	if (arm7_9->need_bypass_before_restart) {
		arm7_9->need_bypass_before_restart = 0;
		arm_jtag_set_instr(jtag_info, 0xf, NULL);
	}
604
	arm_jtag_set_instr(jtag_info, 0x4, NULL);
605
	
mifi's avatar
mifi committed
606
607
608
609
610
611
612
613
614
615
616
617
	if (!set)
	{
		/* check for DBGACK and SYSCOMP set (others don't care) */
		
		/* NB! These are constants that must be available until after next jtag_execute() and
		   we evaluate the values upon first execution in lieu of setting up these constants
		   during early setup.
		*/
		buf_set_u32(check_value, 0, 32, 0x9);
		buf_set_u32(check_mask, 0, 32, 0x9);
		set=1;
	}
618
619
620
621
622
623
624
	
	/* read debug status register */
	embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);

	return ERROR_OK;
}

625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
	u32 *data;
	int i;
	
	data = malloc(size * (sizeof(u32)));
	
	embeddedice_receive(jtag_info, data, size);
	
	for (i = 0; i < size; i++)
	{
		h_u32_to_le(buffer + (i * 4), data[i]);
	}
	
	free(data);
	
	return ERROR_OK;
}

int arm7_9_handle_target_request(void *priv)
{
	target_t *target = priv;
650
651
	if (!target->type->examined)
		return ERROR_OK;
652
653
654
655
656
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	arm_jtag_t *jtag_info = &arm7_9->jtag_info; 
	reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
	
657
	
658
659
660
	if (!target->dbg_msg_enabled)
		return ERROR_OK;
		
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
	if (target->state == TARGET_RUNNING)
	{
		/* read DCC control register */
		embeddedice_read_reg(dcc_control);
		jtag_execute_queue();
		
		/* check W bit */
		if (buf_get_u32(dcc_control->value, 1, 1) == 1)
		{
			u32 request;
			
			embeddedice_receive(jtag_info, &request, 1);
			target_request(target, request);
		}
	}
	
	return ERROR_OK;
}

680
int arm7_9_poll(target_t *target)
681
682
683
684
685
686
687
688
689
690
{
	int retval;
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];

	/* read debug status register */
	embeddedice_read_reg(dbg_stat);
	if ((retval = jtag_execute_queue()) != ERROR_OK)
	{
691
		return retval;
692
693
694
695
	}
	
	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
	{
696
/*		LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
697
		if (target->state == TARGET_UNKNOWN)
698
		{
699
			target->state = TARGET_RUNNING;
700
			LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
701
702
703
		}
		if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
		{
704
705
706
707
708
709
710
711
712
713
714
715
			int check_pc=0;
			if (target->state == TARGET_RESET)
			{
				if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
				{
					if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
					{
						check_pc = 1;
					}
				}
			}
			
716
717
			target->state = TARGET_HALTED;
			
718
719
720
			if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
				return retval;
			
721
722
723
724
725
726
			if (check_pc)
			{
				reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
				u32 t=*((u32 *)reg->value);
				if (t!=0)
				{
727
					LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
728
729
730
				}
			}
			
731
732
733
734
735
736
737
738
739
740
			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
		}
		if (target->state == TARGET_DEBUG_RUNNING)
		{
			target->state = TARGET_HALTED;
			if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
				return retval;
			
			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
		}
741
742
		if (target->state != TARGET_HALTED)
		{
743
			LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
744
		}
745
	}
746
747
748
749
750
751
	else
	{
		if (target->state != TARGET_DEBUG_RUNNING)
			target->state = TARGET_RUNNING;
	}
	
752
	return ERROR_OK;
753
754
}

755
756
757
/*
  Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
  in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
oharboe's avatar
   
oharboe committed
758
  while the core is held in reset(SRST). It isn't possible to program the halt
759
760
761
762
  condition once reset was asserted, hence a hook that allows the target to set
  up its reset-halt condition prior to asserting reset.
*/

763
764
int arm7_9_assert_reset(target_t *target)
{
765
766
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
767
	LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
768
	
769
770
771
772
773
	if (!(jtag_reset_config & RESET_HAS_SRST))
	{
		LOG_ERROR("Can't assert SRST");
		return ERROR_FAIL;
	}
oharboe's avatar
   
oharboe committed
774

oharboe's avatar
   
oharboe committed
775
	if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
776
	{
oharboe's avatar
   
oharboe committed
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
		/*
		 * Some targets do not support communication while SRST is asserted. We need to
		 * set up the reset vector catch here.
		 * 
		 * If TRST is asserted, then these settings will be reset anyway, so setting them
		 * here is harmless.  
		 */
		if (arm7_9->has_vector_catch)
		{
			/* program vector catch register to catch reset vector */
			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
		}
		else
		{
			/* program watchpoint unit to match on reset vector address */
792
			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
oharboe's avatar
   
oharboe committed
793
			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
794
795
796
			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
oharboe's avatar
   
oharboe committed
797
		}
798
799
	}

oharboe's avatar
   
oharboe committed
800
	/* here we should issue a srst only, but we may have to assert trst as well */
801
	if (jtag_reset_config & RESET_SRST_PULLS_TRST)
802
	{
803
804
805
806
		jtag_add_reset(1, 1);
	} else
	{
		jtag_add_reset(0, 1);
807
808
	}
	
oharboe's avatar
   
oharboe committed
809

810
811
	target->state = TARGET_RESET;
	jtag_add_sleep(50000);
oharboe's avatar
   
oharboe committed
812

813
814
815
816
817
818
819
820
	armv4_5_invalidate_core_regs(target);

	return ERROR_OK;

}

int arm7_9_deassert_reset(target_t *target)
{
821
	LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
822
823
824
	
	/* deassert reset lines */
	jtag_add_reset(0, 0);
825
	
826
827
828
	return ERROR_OK;
}

829
830
831
832
833
834
int arm7_9_clear_halt(target_t *target)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
	
835
836
	/* we used DBGRQ only if we didn't come out of reset */
	if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
837
838
839
840
841
842
843
844
	{
		/* program EmbeddedICE Debug Control Register to deassert DBGRQ
		 */
		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);	
		embeddedice_store_reg(dbg_ctrl);
	}
	else
	{
845
		if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
846
		{
847
848
849
850
851
852
853
854
855
856
857
858
			/* if we came out of reset, and vector catch is supported, we used
			 * vector catch to enter debug state
			 * restore the register in that case
			 */
			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
		}
		else
		{
			/* restore registers if watchpoint unit 0 was in use
			 */
			if (arm7_9->wp0_used)
			{
859
860
861
862
				if (arm7_9->debug_entry_from_reset)
				{
					embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
				}
863
864
865
866
867
868
869
870
				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
			}
			/* control value always has to be restored, as it was either disabled, 
			 * or enabled with possibly different bits
			 */
			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
871
872
873
874
875
876
		}
	}
	
	return ERROR_OK;
}

877
878
879
880
881
int arm7_9_soft_reset_halt(struct target_s *target)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
882
	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
883
	int i;
oharboe's avatar
   
oharboe committed
884
	int retval;
885
	
886
	if ((retval=target_halt(target))!=ERROR_OK)
oharboe's avatar
   
oharboe committed
887
		return retval;
888
	
oharboe's avatar
   
oharboe committed
889
	for (i=0; i<10; i++)
890
	{
oharboe's avatar
   
oharboe committed
891
892
		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
			break;
893
		embeddedice_read_reg(dbg_stat);
oharboe's avatar
   
oharboe committed
894
895
896
897
898
899
900
901
		if ((retval=jtag_execute_queue())!=ERROR_OK)
			return retval;
		/* do not eat all CPU, time out after 1 se*/
		usleep(100*1000);
		
	}
	if (i==10)
	{
902
		LOG_ERROR("Failed to halt CPU after 1 sec");
oharboe's avatar
   
oharboe committed
903
		return ERROR_TARGET_TIMEOUT;
904
905
906
	}
	target->state = TARGET_HALTED;
	
907
908
909
910
911
912
913
914
915
916
917
918
919
920
	/* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
	 * ensure that DBGRQ is cleared
	 */
	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
	embeddedice_store_reg(dbg_ctrl);
	
	arm7_9_clear_halt(target);
	
	/* if the target is in Thumb state, change to ARM state */
	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
	{
		u32 r0_thumb, pc_thumb;
921
		LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
922
923
924
925
926
		/* Entered debug from Thumb mode */
		armv4_5->core_state = ARMV4_5_STATE_THUMB;
		arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
	}
	
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
	/* all register content is now invalid */
	armv4_5_invalidate_core_regs(target);
	
	/* SVC, ARM state, IRQ and FIQ disabled */
	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
	
	/* start fetching from 0x0 */
	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
	armv4_5->core_cache->reg_list[15].dirty = 1;
	armv4_5->core_cache->reg_list[15].valid = 1;
	
	armv4_5->core_mode = ARMV4_5_MODE_SVC;
	armv4_5->core_state = ARMV4_5_STATE_ARM;
942
943
944

	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
		return ERROR_FAIL;
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
	
	/* reset registers */
	for (i = 0; i <= 14; i++)
	{	
		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
	}
	
	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
	
	return ERROR_OK;
}

int arm7_9_halt(target_t *target)
{
	armv4_5_common_t *armv4_5 = target->arch_info;
	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
	
965
	LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
966
967
968
	
	if (target->state == TARGET_HALTED)
	{
969
		LOG_DEBUG("target was already halted");
oharboe's avatar
   
oharboe committed
970
		return ERROR_OK;
971
	}
972
973
974
	
	if (target->state == TARGET_UNKNOWN)
	{
975
		LOG_WARNING("target was in unknown state when halt was requested");
976
	}
977
	
978
	if (target->state == TARGET_RESET) 
979
	{
980
981
		if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
		{
982
			LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
983
984
			return ERROR_TARGET_FAILURE;
		}
985
986
987
		else
		{
			/* we came here in a reset_halt or reset_init sequence
988
			 * debug entry was already prepared in arm7_9_assert_reset()
989
990
991
992
993
			 */
			target->debug_reason = DBG_REASON_DBGRQ;
			
			return ERROR_OK; 
		}
994
	}
995
996
997
998
999

	if (arm7_9->use_dbgrq)
	{
		/* program EmbeddedICE Debug Control Register to assert DBGRQ
		 */
oharboe's avatar
oharboe committed
1000
		if (arm7_9->set_special_dbgrq) {
For faster browsing, not all history is shown. View entire blame