stm32x.c 32.5 KB
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/***************************************************************************
 *   Copyright (C) 2005 by Dominic Rath                                    *
 *   Dominic.Rath@gmx.de                                                   *
 *                                                                         *
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 *   Copyright (C) 2008 by Spencer Oliver                                  *
 *   spen@spen-soft.co.uk                                                  *
 *                                                                         *
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 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 ***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

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#include "imp.h"
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#include "stm32x.h"
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#include <helper/binarybuffer.h>
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#include <target/algorithm.h>
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#include <target/armv7m.h>
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static int stm32x_mass_erase(struct flash_bank *bank);
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/* flash bank stm32x <base> <size> 0 0 <target#>
 */
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FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
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{
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	struct stm32x_flash_bank *stm32x_info;
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	if (CMD_ARGC < 6)
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	{
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		LOG_WARNING("incomplete flash_bank stm32x configuration");
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		return ERROR_FLASH_BANK_INVALID;
	}
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	stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
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	bank->driver_priv = stm32x_info;
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	stm32x_info->write_algorithm = NULL;
	stm32x_info->probed = 0;
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	return ERROR_OK;
}

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static uint32_t stm32x_get_flash_status(struct flash_bank *bank)
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{
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	struct target *target = bank->target;
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	uint32_t status;
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	target_read_u32(target, STM32_FLASH_SR, &status);
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	return status;
}

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static uint32_t stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
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{
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	struct target *target = bank->target;
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	uint32_t status;
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	/* wait for busy to clear */
	while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
	{
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		LOG_DEBUG("status: 0x%" PRIx32 "", status);
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		alive_sleep(1);
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	}
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	/* Clear but report errors */
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	if (status & (FLASH_WRPRTERR | FLASH_PGERR))
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	{
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		target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
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	}
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	return status;
}

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static int stm32x_read_options(struct flash_bank *bank)
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{
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	uint32_t optiondata;
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	struct stm32x_flash_bank *stm32x_info = NULL;
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	struct target *target = bank->target;
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	stm32x_info = bank->driver_priv;
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	/* read current option bytes */
	target_read_u32(target, STM32_FLASH_OBR, &optiondata);
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	stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
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	stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
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	if (optiondata & (1 << OPT_READOUT))
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		LOG_INFO("Device Security Bit Set");
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	/* each bit refers to a 4bank protection */
	target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
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	stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
	stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
	stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
	stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
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	return ERROR_OK;
}

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static int stm32x_erase_options(struct flash_bank *bank)
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{
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	struct stm32x_flash_bank *stm32x_info = NULL;
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	struct target *target = bank->target;
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	uint32_t status;
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	stm32x_info = bank->driver_priv;
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	/* read current options */
	stm32x_read_options(bank);
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	/* unlock flash registers */
	target_write_u32(target, STM32_FLASH_KEYR, KEY1);
	target_write_u32(target, STM32_FLASH_KEYR, KEY2);
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	/* unlock option flash registers */
	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
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	/* erase option bytes */
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	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
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	status = stm32x_wait_status_busy(bank, 10);
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	if (status & FLASH_WRPRTERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	if (status & FLASH_PGERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	/* clear readout protection and complementary option bytes
	 * this will also force a device unlock if set */
	stm32x_info->option_bytes.RDP = 0x5AA5;
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	return ERROR_OK;
}

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static int stm32x_write_options(struct flash_bank *bank)
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{
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	struct stm32x_flash_bank *stm32x_info = NULL;
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	struct target *target = bank->target;
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	uint32_t status;
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	stm32x_info = bank->driver_priv;
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	/* unlock flash registers */
	target_write_u32(target, STM32_FLASH_KEYR, KEY1);
	target_write_u32(target, STM32_FLASH_KEYR, KEY2);
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	/* unlock option flash registers */
	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
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	/* program option bytes */
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	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
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	/* write user option byte */
	target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
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	status = stm32x_wait_status_busy(bank, 10);
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	if (status & FLASH_WRPRTERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	if (status & FLASH_PGERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	/* write protection byte 1 */
	target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
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	status = stm32x_wait_status_busy(bank, 10);
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	if (status & FLASH_WRPRTERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	if (status & FLASH_PGERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	/* write protection byte 2 */
	target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
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	status = stm32x_wait_status_busy(bank, 10);
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	if (status & FLASH_WRPRTERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	if (status & FLASH_PGERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	/* write protection byte 3 */
	target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
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	status = stm32x_wait_status_busy(bank, 10);
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	if (status & FLASH_WRPRTERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	if (status & FLASH_PGERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	/* write protection byte 4 */
	target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
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	status = stm32x_wait_status_busy(bank, 10);
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	if (status & FLASH_WRPRTERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	if (status & FLASH_PGERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	/* write readout protection bit */
	target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
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	status = stm32x_wait_status_busy(bank, 10);
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	if (status & FLASH_WRPRTERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	if (status & FLASH_PGERR)
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		return ERROR_FLASH_OPERATION_FAILED;
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	target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
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	return ERROR_OK;
}

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static int stm32x_protect_check(struct flash_bank *bank)
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{
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	struct target *target = bank->target;
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	struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
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	uint32_t protection;
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	int i, s;
	int num_bits;
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	int set;
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	if (target->state != TARGET_HALTED)
	{
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		LOG_ERROR("Target not halted");
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		return ERROR_TARGET_NOT_HALTED;
	}
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	/* medium density - each bit refers to a 4bank protection
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	 * high density - each bit refers to a 2bank protection */
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	target_read_u32(target, STM32_FLASH_WRPR, &protection);
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	/* medium density - each protection bit is for 4 * 1K pages
	 * high density - each protection bit is for 2 * 2K pages */
	num_bits = (bank->num_sectors / stm32x_info->ppage_size);
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	if (stm32x_info->ppage_size == 2)
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	{
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		/* high density flash/connectivity line protection */
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		set = 1;
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		if (protection & (1 << 31))
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			set = 0;
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		/* bit 31 controls sector 62 - 255 protection for high density
		 * bit 31 controls sector 62 - 127 protection for connectivity line */
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		for (s = 62; s < bank->num_sectors; s++)
		{
			bank->sectors[s].is_protected = set;
		}
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		if (bank->num_sectors > 61)
			num_bits = 31;
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		for (i = 0; i < num_bits; i++)
		{
			set = 1;
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			if (protection & (1 << i))
				set = 0;
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			for (s = 0; s < stm32x_info->ppage_size; s++)
				bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
		}
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	}
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	else
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	{
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		/* low/medium density flash protection */
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		for (i = 0; i < num_bits; i++)
		{
			set = 1;
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			if (protection & (1 << i))
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				set = 0;
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			for (s = 0; s < stm32x_info->ppage_size; s++)
				bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
		}
	}
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	return ERROR_OK;
}

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static int stm32x_erase(struct flash_bank *bank, int first, int last)
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{
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	struct target *target = bank->target;
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	int i;
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	uint32_t status;
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	if (bank->target->state != TARGET_HALTED)
	{
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		LOG_ERROR("Target not halted");
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		return ERROR_TARGET_NOT_HALTED;
	}
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	if ((first == 0) && (last == (bank->num_sectors - 1)))
	{
		return stm32x_mass_erase(bank);
	}
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	/* unlock flash registers */
	target_write_u32(target, STM32_FLASH_KEYR, KEY1);
	target_write_u32(target, STM32_FLASH_KEYR, KEY2);
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	for (i = first; i <= last; i++)
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	{
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		target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
		target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
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		target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
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		status = stm32x_wait_status_busy(bank, 10);
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		if (status & FLASH_WRPRTERR)
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			return ERROR_FLASH_OPERATION_FAILED;
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		if (status & FLASH_PGERR)
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			return ERROR_FLASH_OPERATION_FAILED;
		bank->sectors[i].is_erased = 1;
	}

	target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
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	return ERROR_OK;
}

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static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
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{
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	struct stm32x_flash_bank *stm32x_info = NULL;
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	struct target *target = bank->target;
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	uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
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	int i, reg, bit;
	int status;
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	uint32_t protection;
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	stm32x_info = bank->driver_priv;
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	if (target->state != TARGET_HALTED)
	{
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		LOG_ERROR("Target not halted");
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		return ERROR_TARGET_NOT_HALTED;
	}
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	if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
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	{
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		LOG_WARNING("Error: start and end sectors must be on a %d sector boundary", stm32x_info->ppage_size);
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		return ERROR_FLASH_SECTOR_INVALID;
	}
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	/* medium density - each bit refers to a 4bank protection
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	 * high density - each bit refers to a 2bank protection */
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	target_read_u32(target, STM32_FLASH_WRPR, &protection);
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	prot_reg[0] = (uint16_t)protection;
	prot_reg[1] = (uint16_t)(protection >> 8);
	prot_reg[2] = (uint16_t)(protection >> 16);
	prot_reg[3] = (uint16_t)(protection >> 24);
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	if (stm32x_info->ppage_size == 2)
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	{
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		/* high density flash */
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		/* bit 7 controls sector 62 - 255 protection */
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		if (last > 61)
		{
			if (set)
				prot_reg[3] &= ~(1 << 7);
			else
				prot_reg[3] |= (1 << 7);
		}
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		if (first > 61)
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			first = 62;
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		if (last > 61)
			last = 61;
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		for (i = first; i <= last; i++)
		{
			reg = (i / stm32x_info->ppage_size) / 8;
			bit = (i / stm32x_info->ppage_size) - (reg * 8);
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			if (set)
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				prot_reg[reg] &= ~(1 << bit);
			else
				prot_reg[reg] |= (1 << bit);
		}
	}
	else
	{
		/* medium density flash */
		for (i = first; i <= last; i++)
		{
			reg = (i / stm32x_info->ppage_size) / 8;
			bit = (i / stm32x_info->ppage_size) - (reg * 8);
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			if (set)
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				prot_reg[reg] &= ~(1 << bit);
			else
				prot_reg[reg] |= (1 << bit);
		}
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	}
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	if ((status = stm32x_erase_options(bank)) != ERROR_OK)
		return status;
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	stm32x_info->option_bytes.protection[0] = prot_reg[0];
	stm32x_info->option_bytes.protection[1] = prot_reg[1];
	stm32x_info->option_bytes.protection[2] = prot_reg[2];
	stm32x_info->option_bytes.protection[3] = prot_reg[3];
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	return stm32x_write_options(bank);
}

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static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
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{
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	struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
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	struct target *target = bank->target;
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	uint32_t buffer_size = 16384;
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	struct working_area *source;
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	uint32_t address = bank->base + offset;
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	struct reg_param reg_params[4];
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	struct armv7m_algorithm armv7m_info;
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	int retval = ERROR_OK;
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	uint8_t stm32x_flash_write_code[] = {
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									/* write: */
		0xDF, 0xF8, 0x24, 0x40,		/* ldr	r4, STM32_FLASH_CR */
		0x09, 0x4D,					/* ldr	r5, STM32_FLASH_SR */
		0x4F, 0xF0, 0x01, 0x03,		/* mov	r3, #1 */
		0x23, 0x60,					/* str	r3, [r4, #0] */
		0x30, 0xF8, 0x02, 0x3B,		/* ldrh r3, [r0], #2 */
		0x21, 0xF8, 0x02, 0x3B,		/* strh r3, [r1], #2 */
									/* busy: */
		0x2B, 0x68,					/* ldr 	r3, [r5, #0] */
		0x13, 0xF0, 0x01, 0x0F,		/* tst 	r3, #0x01 */
		0xFB, 0xD0,					/* beq 	busy */
		0x13, 0xF0, 0x14, 0x0F,		/* tst	r3, #0x14 */
		0x01, 0xD1,					/* bne	exit */
		0x01, 0x3A,					/* subs	r2, r2, #1 */
		0xED, 0xD1,					/* bne	write */
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		0x00, 0xBE,     			/* bkpt #0 */
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		0x10, 0x20, 0x02, 0x40,		/* STM32_FLASH_CR:	.word 0x40022010 */
		0x0C, 0x20, 0x02, 0x40		/* STM32_FLASH_SR:	.word 0x4002200C */
	};
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	/* flash write code */
	if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
	{
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		LOG_WARNING("no working area available, can't do block memory writes");
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		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	};
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	if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK)
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		return retval;
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	/* memory buffer */
	while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
	{
		buffer_size /= 2;
		if (buffer_size <= 256)
		{
			/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
			if (stm32x_info->write_algorithm)
				target_free_working_area(target, stm32x_info->write_algorithm);
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			LOG_WARNING("no large enough working area available, can't do block memory writes");
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			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
		}
	};
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	armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
	armv7m_info.core_mode = ARMV7M_MODE_ANY;
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	init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
	init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
	init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
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	while (count > 0)
	{
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		uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
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		if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer)) != ERROR_OK)
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			break;
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		buf_set_u32(reg_params[0].value, 0, 32, source->address);
		buf_set_u32(reg_params[1].value, 0, 32, address);
		buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
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		if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
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				stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
		{
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			LOG_ERROR("error executing stm32x flash write algorithm");
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			retval = ERROR_FLASH_OPERATION_FAILED;
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			break;
		}
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		if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
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		{
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			LOG_ERROR("flash memory not erased before writing");
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			/* Clear but report errors */
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			target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
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			retval = ERROR_FLASH_OPERATION_FAILED;
			break;
		}
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		if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
		{
			LOG_ERROR("flash memory write protected");
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			/* Clear but report errors */
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			target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
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			retval = ERROR_FLASH_OPERATION_FAILED;
			break;
		}
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		buffer += thisrun_count * 2;
		address += thisrun_count * 2;
		count -= thisrun_count;
	}
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	target_free_working_area(target, source);
	target_free_working_area(target, stm32x_info->write_algorithm);
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	destroy_reg_param(&reg_params[0]);
	destroy_reg_param(&reg_params[1]);
	destroy_reg_param(&reg_params[2]);
	destroy_reg_param(&reg_params[3]);
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	return retval;
}

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static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
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{
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	struct target *target = bank->target;
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	uint32_t words_remaining = (count / 2);
	uint32_t bytes_remaining = (count & 0x00000001);
	uint32_t address = bank->base + offset;
	uint32_t bytes_written = 0;
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	uint8_t status;
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	int retval;
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	if (bank->target->state != TARGET_HALTED)
	{
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		LOG_ERROR("Target not halted");
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		return ERROR_TARGET_NOT_HALTED;
	}

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	if (offset & 0x1)
	{
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		LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
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		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
	}
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	/* unlock flash registers */
	target_write_u32(target, STM32_FLASH_KEYR, KEY1);
	target_write_u32(target, STM32_FLASH_KEYR, KEY2);
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	/* multiple half words (2-byte) to be programmed? */
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	if (words_remaining > 0)
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	{
		/* try using a block write */
		if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
		{
			if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
			{
				/* if block write failed (no sufficient working area),
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				 * we use normal (slow) single dword accesses */
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				LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
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			}
			else if (retval == ERROR_FLASH_OPERATION_FAILED)
			{
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				LOG_ERROR("flash writing failed with error code: 0x%x", retval);
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				return ERROR_FLASH_OPERATION_FAILED;
			}
		}
		else
		{
			buffer += words_remaining * 2;
			address += words_remaining * 2;
			words_remaining = 0;
		}
	}

	while (words_remaining > 0)
	{
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		uint16_t value;
		memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
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		target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
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		target_write_u16(target, address, value);
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		status = stm32x_wait_status_busy(bank, 5);
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		if (status & FLASH_WRPRTERR)
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		{
			LOG_ERROR("flash memory not erased before writing");
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			return ERROR_FLASH_OPERATION_FAILED;
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		}
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		if (status & FLASH_PGERR)
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		{
			LOG_ERROR("flash memory write protected");
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			return ERROR_FLASH_OPERATION_FAILED;
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		}
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		bytes_written += 2;
		words_remaining--;
		address += 2;
	}
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	if (bytes_remaining)
	{
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		uint16_t value = 0xffff;
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		memcpy(&value, buffer + bytes_written, bytes_remaining);

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		target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
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		target_write_u16(target, address, value);
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		status = stm32x_wait_status_busy(bank, 5);
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		if (status & FLASH_WRPRTERR)
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		{
			LOG_ERROR("flash memory not erased before writing");
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			return ERROR_FLASH_OPERATION_FAILED;
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		}
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		if (status & FLASH_PGERR)
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		{
			LOG_ERROR("flash memory write protected");
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			return ERROR_FLASH_OPERATION_FAILED;
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		}
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	}
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	target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
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	return ERROR_OK;
}

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static int stm32x_probe(struct flash_bank *bank)
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{
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	struct target *target = bank->target;
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	struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
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	int i;
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	uint16_t num_pages;
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	uint32_t device_id;
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	int page_size;
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	if (bank->target->state != TARGET_HALTED)
	{
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		LOG_ERROR("Target not halted");
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		return ERROR_TARGET_NOT_HALTED;
	}

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	stm32x_info->probed = 0;
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	/* read stm32 device id register */
	target_read_u32(target, 0xE0042000, &device_id);
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	LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
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	/* get flash size from target */
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	if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
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	{
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		/* failed reading flash size, default to max target family */
		num_pages = 0xffff;
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	}
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	if ((device_id & 0x7ff) == 0x410)
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	{
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		/* medium density - we have 1k pages
		 * 4 pages for a protection area */
		page_size = 1024;
		stm32x_info->ppage_size = 4;
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		/* check for early silicon */
		if (num_pages == 0xffff)
		{
			/* number of sectors incorrect on revA */
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			LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
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			num_pages = 128;
		}
	}
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	else if ((device_id & 0x7ff) == 0x412)
	{
		/* low density - we have 1k pages
		 * 4 pages for a protection area */
		page_size = 1024;
		stm32x_info->ppage_size = 4;
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		/* check for early silicon */
		if (num_pages == 0xffff)
		{
			/* number of sectors incorrect on revA */
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			LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
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			num_pages = 32;
		}
	}
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	else if ((device_id & 0x7ff) == 0x414)
	{
		/* high density - we have 2k pages
		 * 2 pages for a protection area */
		page_size = 2048;
		stm32x_info->ppage_size = 2;
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		/* check for early silicon */
		if (num_pages == 0xffff)
		{
			/* number of sectors incorrect on revZ */
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			LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
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			num_pages = 512;
		}
	}
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	else if ((device_id & 0x7ff) == 0x418)
	{
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		/* connectivity line density - we have 2k pages
		 * 2 pages for a protection area */
		page_size = 2048;
		stm32x_info->ppage_size = 2;
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		/* check for early silicon */
		if (num_pages == 0xffff)
		{
			/* number of sectors incorrect on revZ */
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			LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
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			num_pages = 256;
		}
	}
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	else if ((device_id & 0x7ff) == 0x420)
	{
		/* value line density - we have 1k pages
		 * 4 pages for a protection area */
		page_size = 1024;
		stm32x_info->ppage_size = 4;

		/* check for early silicon */
		if (num_pages == 0xffff)
		{
			/* number of sectors may be incorrrect on early silicon */
			LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
			num_pages = 128;
		}
	}
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	else
	{
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		LOG_WARNING("Cannot identify target as a STM32 family.");
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		return ERROR_FLASH_OPERATION_FAILED;
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	}
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	LOG_INFO("flash size = %dkbytes", num_pages);
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	/* calculate numbers of pages */
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	num_pages /= (page_size / 1024);
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	bank->base = 0x08000000;
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	bank->size = (num_pages * page_size);
	bank->num_sectors = num_pages;