at91sam3.c 74.8 KB
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/***************************************************************************
 *   Copyright (C) 2009 by Duane Ellis                                     *
 *   openocd@duaneellis.com                                                *
 *                                                                         *
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 *   Copyright (C) 2010 by Olaf Lüke (at91sam3s* support)                  *
 *   olaf@uni-paderborn.de                                                 *
 *                                                                         *
 *                                                                         *
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 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the         *
 *   GNU General public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
****************************************************************************/

/* Some of the the lower level code was based on code supplied by
 * ATMEL under this copyright. */

/* BEGIN ATMEL COPYRIGHT */
/* ----------------------------------------------------------------------------
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 *         ATMEL Microcontroller Software Support
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 * ----------------------------------------------------------------------------
 * Copyright (c) 2009, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */
/* END ATMEL COPYRIGHT */

#ifdef HAVE_CONFIG_H
#include "config.h"
#endif


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#include "imp.h"
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#include <helper/time_support.h>
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#define REG_NAME_WIDTH  (12)

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// at91sam3u series (has one or two flash banks)
#define FLASH_BANK0_BASE_U   0x00080000
#define FLASH_BANK1_BASE_U   0x00100000
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// at91sam3s series (has always one flash bank)
#define FLASH_BANK_BASE_S   0x00400000
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// at91sam3n series (has always one flash bank)
#define FLASH_BANK_BASE_N   0x00400000

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#define 	AT91C_EFC_FCMD_GETD                 (0x0) // (EFC) Get Flash Descriptor
#define 	AT91C_EFC_FCMD_WP                   (0x1) // (EFC) Write Page
#define 	AT91C_EFC_FCMD_WPL                  (0x2) // (EFC) Write Page and Lock
#define 	AT91C_EFC_FCMD_EWP                  (0x3) // (EFC) Erase Page and Write Page
#define 	AT91C_EFC_FCMD_EWPL                 (0x4) // (EFC) Erase Page and Write Page then Lock
#define 	AT91C_EFC_FCMD_EA                   (0x5) // (EFC) Erase All
// cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
// #define 	AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane?
// cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
// #define 	AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase pages?
#define 	AT91C_EFC_FCMD_SLB                  (0x8) // (EFC) Set Lock Bit
#define 	AT91C_EFC_FCMD_CLB                  (0x9) // (EFC) Clear Lock Bit
#define 	AT91C_EFC_FCMD_GLB                  (0xA) // (EFC) Get Lock Bit
#define 	AT91C_EFC_FCMD_SFB                  (0xB) // (EFC) Set Fuse Bit
#define 	AT91C_EFC_FCMD_CFB                  (0xC) // (EFC) Clear Fuse Bit
#define 	AT91C_EFC_FCMD_GFB                  (0xD) // (EFC) Get Fuse Bit
#define 	AT91C_EFC_FCMD_STUI                 (0xE) // (EFC) Start Read Unique ID
#define 	AT91C_EFC_FCMD_SPUI                 (0xF) // (EFC) Stop Read Unique ID

#define  offset_EFC_FMR   0
#define  offset_EFC_FCR   4
#define  offset_EFC_FSR   8
#define  offset_EFC_FRR   12


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extern struct flash_driver at91sam3_flash;
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static float
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_tomhz(uint32_t freq_hz)
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{
	float f;

	f = ((float)(freq_hz)) / 1000000.0;
	return f;
}

// How the chip is configured.
struct sam3_cfg {
	uint32_t unique_id[4];

	uint32_t slow_freq;
	uint32_t rc_freq;
	uint32_t mainosc_freq;
	uint32_t plla_freq;
	uint32_t mclk_freq;
	uint32_t cpu_freq;
	uint32_t fclk_freq;
	uint32_t pclk0_freq;
	uint32_t pclk1_freq;
	uint32_t pclk2_freq;


#define SAM3_CHIPID_CIDR          (0x400E0740)
	uint32_t CHIPID_CIDR;
#define SAM3_CHIPID_EXID          (0x400E0744)
	uint32_t CHIPID_EXID;

#define SAM3_SUPC_CR              (0x400E1210)
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	uint32_t SUPC_CR;
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#define SAM3_PMC_BASE             (0x400E0400)
#define SAM3_PMC_SCSR             (SAM3_PMC_BASE + 0x0008)
	uint32_t PMC_SCSR;
#define SAM3_PMC_PCSR             (SAM3_PMC_BASE + 0x0018)
	uint32_t PMC_PCSR;
#define SAM3_CKGR_UCKR            (SAM3_PMC_BASE + 0x001c)
	uint32_t CKGR_UCKR;
#define SAM3_CKGR_MOR             (SAM3_PMC_BASE + 0x0020)
	uint32_t CKGR_MOR;
#define SAM3_CKGR_MCFR            (SAM3_PMC_BASE + 0x0024)
	uint32_t CKGR_MCFR;
#define SAM3_CKGR_PLLAR           (SAM3_PMC_BASE + 0x0028)
	uint32_t CKGR_PLLAR;
#define SAM3_PMC_MCKR             (SAM3_PMC_BASE + 0x0030)
	uint32_t PMC_MCKR;
#define SAM3_PMC_PCK0             (SAM3_PMC_BASE + 0x0040)
	uint32_t PMC_PCK0;
#define SAM3_PMC_PCK1             (SAM3_PMC_BASE + 0x0044)
	uint32_t PMC_PCK1;
#define SAM3_PMC_PCK2             (SAM3_PMC_BASE + 0x0048)
	uint32_t PMC_PCK2;
#define SAM3_PMC_SR               (SAM3_PMC_BASE + 0x0068)
	uint32_t PMC_SR;
#define SAM3_PMC_IMR              (SAM3_PMC_BASE + 0x006c)
	uint32_t PMC_IMR;
#define SAM3_PMC_FSMR             (SAM3_PMC_BASE + 0x0070)
	uint32_t PMC_FSMR;
#define SAM3_PMC_FSPR             (SAM3_PMC_BASE + 0x0074)
	uint32_t PMC_FSPR;
};

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/*
 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
 * the flash wait state (FWS) should be set to 6. It seems like that the
 * cause of the problem is not the flash itself, but the flash write
 * buffer. Ie the wait states have to be set before writing into the
 * buffer.
 * Tested and confirmed with SAM3N and SAM3U
 */
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struct sam3_bank_private {
	int probed;
	// DANGER: THERE ARE DRAGONS HERE..
	// NOTE: If you add more 'ghost' pointers
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	// be aware that you must *manually* update
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	// these pointers in the function sam3_GetDetails()
	// See the comment "Here there be dragons"

	// so we can find the chip we belong to
	struct sam3_chip *pChip;
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	// so we can find the orginal bank pointer
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	struct flash_bank *pBank;
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	unsigned bank_number;
	uint32_t controller_address;
	uint32_t base_address;
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	uint32_t flash_wait_states;
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	bool present;
	unsigned size_bytes;
	unsigned nsectors;
	unsigned sector_size;
	unsigned page_size;
};

struct sam3_chip_details {
	// THERE ARE DRAGONS HERE..
	// note: If you add pointers here
	// becareful about them as they
	// may need to be updated inside
	// the function: "sam3_GetDetails()
	// which copy/overwrites the
	// 'runtime' copy of this structure
	uint32_t chipid_cidr;
	const char *name;

	unsigned n_gpnvms;
#define SAM3_N_NVM_BITS 3
	unsigned  gpnvm[SAM3_N_NVM_BITS];
	unsigned  total_flash_size;
	unsigned  total_sram_size;
	unsigned  n_banks;
#define SAM3_MAX_FLASH_BANKS 2
	// these are "initialized" from the global const data
	struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
};


struct sam3_chip {
	struct sam3_chip *next;
	int    probed;

	// this is "initialized" from the global const structure
	struct sam3_chip_details details;
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	struct target *target;
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	struct sam3_cfg cfg;
};


struct sam3_reg_list {
	uint32_t address;  size_t struct_offset; const char *name;
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	void (*explain_func)(struct sam3_chip *pInfo);
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};


static struct sam3_chip *all_sam3_chips;

static struct sam3_chip *
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get_current_sam3(struct command_context *cmd_ctx)
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{
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	struct target *t;
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	static struct sam3_chip *p;

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	t = get_current_target(cmd_ctx);
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	if (!t) {
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		command_print(cmd_ctx, "No current target?");
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		return NULL;
	}

	p = all_sam3_chips;
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	if (!p) {
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		// this should not happen
		// the command is not registered until the chip is created?
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		command_print(cmd_ctx, "No SAM3 chips exist?");
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		return NULL;
	}

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	while (p) {
		if (p->target == t) {
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			return p;
		}
		p = p->next;
	}
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	command_print(cmd_ctx, "Cannot find SAM3 chip?");
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	return NULL;
}


// these are used to *initialize* the "pChip->details" structure.
static const struct sam3_chip_details all_sam3_details[] = {
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	// Start at91sam3u* series
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	{
		.chipid_cidr    = 0x28100960,
		.name           = "at91sam3u4e",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 52 * 1024,
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		.n_gpnvms       = 3,
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		.n_banks        = 2,

		// System boots at address 0x0
		// gpnvm[1] = selects boot code
		//     if gpnvm[1] == 0
		//         boot is via "SAMBA" (rom)
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		//     else
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		//         boot is via FLASH
		//         Selection is via gpnvm[2]
		//     endif
		//
		// NOTE: banks 0 & 1 switch places
		//     if gpnvm[2] == 0
		//         Bank0 is the boot rom
		//      else
		//         Bank1 is the boot rom
		//      endif
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//		.bank[0] = {
		{
		  {
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			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
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			.base_address = FLASH_BANK0_BASE_U,
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			.controller_address = 0x400e0800,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes = 128 * 1024,
			.nsectors   = 16,
			.sector_size = 8192,
			.page_size   = 256,
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		  },
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//		.bank[1] = {
		  {
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			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 1,
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			.base_address = FLASH_BANK1_BASE_U,
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			.controller_address = 0x400e0a00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes = 128 * 1024,
			.nsectors   = 16,
			.sector_size = 8192,
			.page_size   = 256,
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		  },
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		},
	},

	{
		.chipid_cidr    = 0x281a0760,
		.name           = "at91sam3u2e",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      =  36 * 1024,
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		.n_gpnvms       = 2,
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		.n_banks        = 1,

		// System boots at address 0x0
		// gpnvm[1] = selects boot code
		//     if gpnvm[1] == 0
		//         boot is via "SAMBA" (rom)
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		//     else
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		//         boot is via FLASH
		//         Selection is via gpnvm[2]
		//     endif
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//		.bank[0] = {
		{
		  {
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			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
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			.base_address = FLASH_BANK0_BASE_U,
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			.controller_address = 0x400e0800,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes = 128 * 1024,
			.nsectors   = 16,
			.sector_size = 8192,
			.page_size   = 256,
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		  },
//		  .bank[1] = {
		  {
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			.present = 0,
			.probed = 0,
			.bank_number = 1,
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		  },
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		},
	},
	{
		.chipid_cidr    = 0x28190560,
		.name           = "at91sam3u1e",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 20 * 1024,
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		.n_gpnvms       = 2,
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		.n_banks        = 1,

		// System boots at address 0x0
		// gpnvm[1] = selects boot code
		//     if gpnvm[1] == 0
		//         boot is via "SAMBA" (rom)
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		//     else
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		//         boot is via FLASH
		//         Selection is via gpnvm[2]
		//     endif
		//
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//		.bank[0] = {
		{
		  {
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			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
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			.base_address = FLASH_BANK0_BASE_U,
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			.controller_address = 0x400e0800,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes =  64 * 1024,
			.nsectors   =  8,
			.sector_size = 8192,
			.page_size   = 256,
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		  },
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//		.bank[1] = {
		  {
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			.present = 0,
			.probed = 0,
			.bank_number = 1,
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		  },
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		},
	},
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	{
		.chipid_cidr    = 0x28000960,
		.name           = "at91sam3u4c",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 52 * 1024,
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		.n_gpnvms       = 3,
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		.n_banks        = 2,

		// System boots at address 0x0
		// gpnvm[1] = selects boot code
		//     if gpnvm[1] == 0
		//         boot is via "SAMBA" (rom)
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		//     else
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		//         boot is via FLASH
		//         Selection is via gpnvm[2]
		//     endif
		//
		// NOTE: banks 0 & 1 switch places
		//     if gpnvm[2] == 0
		//         Bank0 is the boot rom
		//      else
		//         Bank1 is the boot rom
		//      endif
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		{
		  {
//		.bank[0] = {
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			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
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			.base_address = FLASH_BANK0_BASE_U,
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			.controller_address = 0x400e0800,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes = 128 * 1024,
			.nsectors   = 16,
			.sector_size = 8192,
			.page_size   = 256,
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		  },
//		.bank[1] = {
		  {
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			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 1,
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			.base_address = FLASH_BANK1_BASE_U,
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			.controller_address = 0x400e0a00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes = 128 * 1024,
			.nsectors   = 16,
			.sector_size = 8192,
			.page_size   = 256,
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		  },
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		},
	},

	{
		.chipid_cidr    = 0x280a0760,
		.name           = "at91sam3u2c",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 36 * 1024,
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		.n_gpnvms       = 2,
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		.n_banks        = 1,

		// System boots at address 0x0
		// gpnvm[1] = selects boot code
		//     if gpnvm[1] == 0
		//         boot is via "SAMBA" (rom)
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		//     else
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		//         boot is via FLASH
		//         Selection is via gpnvm[2]
		//     endif
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		{
//		.bank[0] = {
		  {
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			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
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			.base_address = FLASH_BANK0_BASE_U,
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			.controller_address = 0x400e0800,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes = 128 * 1024,
			.nsectors   = 16,
			.sector_size = 8192,
			.page_size   = 256,
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		  },
//		.bank[1] = {
		  {
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			.present = 0,
			.probed = 0,
			.bank_number = 1,
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		  },
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		},
	},
	{
		.chipid_cidr    = 0x28090560,
		.name           = "at91sam3u1c",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 20 * 1024,
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		.n_gpnvms       = 2,
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		.n_banks        = 1,

		// System boots at address 0x0
		// gpnvm[1] = selects boot code
		//     if gpnvm[1] == 0
		//         boot is via "SAMBA" (rom)
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		//     else
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		//         boot is via FLASH
		//         Selection is via gpnvm[2]
		//     endif
		//
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		{
//		.bank[0] = {
		  {
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			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
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			.base_address = FLASH_BANK0_BASE_U,
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			.controller_address = 0x400e0800,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes =  64 * 1024,
			.nsectors   =  8,
			.sector_size = 8192,
			.page_size   = 256,
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		  },
//		.bank[1] = {
		  {
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			.present = 0,
			.probed = 0,
			.bank_number = 1,
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		  },
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		},
	},

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	// Start at91sam3s* series

	// Note: The preliminary at91sam3s datasheet says on page 302
	// that the flash controller is at address 0x400E0800.
	// This is _not_ the case, the controller resides at address 0x400e0a0.
	{
		.chipid_cidr    = 0x28A00960,
		.name           = "at91sam3s4c",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 48 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
//		.bank[0] = {
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes =  256 * 1024,
			.nsectors   =  32,
			.sector_size = 8192,
			.page_size   = 256,
		  },
//		.bank[1] = {
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},

	{
		.chipid_cidr    = 0x28900960,
		.name           = "at91sam3s4b",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 48 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
//		.bank[0] = {
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes =  256 * 1024,
			.nsectors   =  32,
			.sector_size = 8192,
			.page_size   = 256,
		  },
//		.bank[1] = {
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	{
		.chipid_cidr    = 0x28800960,
		.name           = "at91sam3s4a",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 48 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
//		.bank[0] = {
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes =  256 * 1024,
			.nsectors   =  32,
			.sector_size = 8192,
			.page_size   = 256,
		  },
//		.bank[1] = {
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	{
		.chipid_cidr    = 0x28AA0760,
		.name           = "at91sam3s2c",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 32 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
//		.bank[0] = {
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes =  128 * 1024,
			.nsectors   =  16,
			.sector_size = 8192,
			.page_size   = 256,
		  },
//		.bank[1] = {
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	{
		.chipid_cidr    = 0x289A0760,
		.name           = "at91sam3s2b",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 32 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
//		.bank[0] = {
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes =  128 * 1024,
			.nsectors   =  16,
			.sector_size = 8192,
			.page_size   = 256,
		  },
//		.bank[1] = {
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	{
		.chipid_cidr    = 0x288A0760,
		.name           = "at91sam3s2a",
		.total_flash_size     = 128 * 1024,
		.total_sram_size      = 32 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
//		.bank[0] = {
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes =  128 * 1024,
			.nsectors   =  16,
			.sector_size = 8192,
			.page_size   = 256,
		  },
//		.bank[1] = {
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	{
		.chipid_cidr    = 0x28A90560,
		.name           = "at91sam3s1c",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 16 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
//		.bank[0] = {
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes =  64 * 1024,
			.nsectors   =  8,
			.sector_size = 8192,
			.page_size   = 256,
		  },
//		.bank[1] = {
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	{
		.chipid_cidr    = 0x28990560,
		.name           = "at91sam3s1b",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 16 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
//		.bank[0] = {
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes =  64 * 1024,
			.nsectors   =  8,
			.sector_size = 8192,
			.page_size   = 256,
		  },
//		.bank[1] = {
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
	{
		.chipid_cidr    = 0x28890560,
		.name           = "at91sam3s1a",
		.total_flash_size     = 64 * 1024,
		.total_sram_size      = 16 * 1024,
		.n_gpnvms       = 2,
		.n_banks        = 1,
		{
//		.bank[0] = {
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_S,
			.controller_address = 0x400e0a00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes =  64 * 1024,
			.nsectors   =  8,
			.sector_size = 8192,
			.page_size   = 256,
		  },
//		.bank[1] = {
		  {
			.present = 0,
			.probed = 0,
			.bank_number = 1,

		  },
		},
	},
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	// Start at91sam3n* series
	{
		.chipid_cidr    = 0x29540960,
		.name           = "at91sam3n4c",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 24 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 1,

		// System boots at address 0x0
		// gpnvm[1] = selects boot code
		//     if gpnvm[1] == 0
		//         boot is via "SAMBA" (rom)
		//     else
		//         boot is via FLASH
		//         Selection is via gpnvm[2]
		//     endif
		//
		// NOTE: banks 0 & 1 switch places
		//     if gpnvm[2] == 0
		//         Bank0 is the boot rom
		//      else
		//         Bank1 is the boot rom
		//      endif
//		.bank[0] = {
		{
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_N,
			.controller_address = 0x400e0A00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes = 256 * 1024,
			.nsectors   = 16,
			.sector_size = 16384,
			.page_size   = 256,
		  },

//		.bank[1] = {
		  {
		  	.present = 0,
			.probed = 0,
			.bank_number = 1,
		  },
		},
	},

	{
		.chipid_cidr    = 0x29440960,
		.name           = "at91sam3n4b",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 24 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 1,

		// System boots at address 0x0
		// gpnvm[1] = selects boot code
		//     if gpnvm[1] == 0
		//         boot is via "SAMBA" (rom)
		//     else
		//         boot is via FLASH
		//         Selection is via gpnvm[2]
		//     endif
		//
		// NOTE: banks 0 & 1 switch places
		//     if gpnvm[2] == 0
		//         Bank0 is the boot rom
		//      else
		//         Bank1 is the boot rom
		//      endif
//		.bank[0] = {
		{
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_N,
			.controller_address = 0x400e0A00,
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			.flash_wait_states = 6, /* workaround silicon bug */
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			.present = 1,
			.size_bytes = 256 * 1024,
			.nsectors   = 16,
			.sector_size = 16384,
			.page_size   = 256,
		  },

//		.bank[1] = {
		  {
		  	.present = 0,
			.probed = 0,
			.bank_number = 1,
		  },
		},
	},

	{
		.chipid_cidr    = 0x29340960,
		.name           = "at91sam3n4a",
		.total_flash_size     = 256 * 1024,
		.total_sram_size      = 24 * 1024,
		.n_gpnvms       = 3,
		.n_banks        = 1,

		// System boots at address 0x0
		// gpnvm[1] = selects boot code
		//     if gpnvm[1] == 0
		//         boot is via "SAMBA" (rom)
		//     else
		//         boot is via FLASH
		//         Selection is via gpnvm[2]
		//     endif
		//
		// NOTE: banks 0 & 1 switch places
		//     if gpnvm[2] == 0
		//         Bank0 is the boot rom
		//      else
		//         Bank1 is the boot rom
		//      endif
//		.bank[0] = {
		{
		  {
			.probed = 0,
			.pChip  = NULL,
			.pBank  = NULL,
			.bank_number = 0,
			.base_address = FLASH_BANK_BASE_N,
			.controller_address = 0x400e0A00,
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			.present = 1,
			.size_bytes = 256 * 1024,
			.nsectors   = 16,
			.sector_size = 16384,
			.page_size   = 256,
		  },

//		.bank[1] = {
		  {
		  	.present = 0,
			.probed = 0,
			.bank_number = 1,
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