Commit 2f174c1f authored by schneider's avatar schneider
Browse files

feat(fundamental): Copy rev1 files to rev2 folder

parent 954b2927
EESchema-DOCLIB Version 2.0
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
#End Doc Library
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# DMC3400SDW
#
DEF DMC3400SDW T 0 40 Y Y 2 L N
F0 "T" -250 -50 50 H V C CNN
F1 "DMC3400SDW" -100 100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C -485 450 111 1 1 10 N
C -450 380 11 1 1 0 F
C -450 520 11 1 1 0 F
C 215 450 111 1 1 10 N
C 250 380 11 1 1 0 F
C 250 520 11 1 1 0 F
P 2 1 1 0 -650 450 -540 450 N
P 2 1 1 0 -520 380 -450 380 N
P 2 1 1 10 -520 400 -520 360 N
P 2 1 1 0 -520 450 -450 450 N
P 2 1 1 10 -520 470 -520 430 N
P 2 1 1 0 -520 520 -450 520 N
P 2 1 1 10 -520 540 -520 500 N
P 2 1 1 0 -450 380 -450 350 N
P 2 1 1 0 -450 380 -450 450 N
P 2 1 1 0 -450 550 -450 520 N
P 2 1 1 0 50 450 160 450 N
P 2 1 1 0 180 380 250 380 N
P 2 1 1 10 180 400 180 360 N
P 2 1 1 0 180 450 250 450 N
P 2 1 1 10 180 470 180 430 N
P 2 1 1 0 180 520 250 520 N
P 2 1 1 10 180 540 180 500 N
P 2 1 1 0 250 380 250 350 N
P 2 1 1 0 250 380 250 450 N
P 2 1 1 0 250 550 250 520 N
P 3 1 1 10 -540 525 -540 375 -540 375 N
P 3 1 1 10 160 525 160 375 160 375 N
P 4 1 1 0 -510 450 -470 465 -470 435 -510 450 F
P 4 1 1 0 -450 380 -420 380 -420 520 -450 520 N
P 4 1 1 0 -440 470 -435 465 -405 465 -400 460 N
P 4 1 1 0 -420 465 -435 440 -405 440 -420 465 N
P 4 1 1 0 240 450 200 435 200 465 240 450 F
P 4 1 1 0 250 380 280 380 280 520 250 520 N
P 4 1 1 0 260 430 265 435 295 435 300 440 N
P 4 1 1 0 280 435 265 460 295 460 280 435 N
X D1 D1 -450 650 100 D 50 50 1 1 P
X D2 D2 250 650 100 D 50 50 1 1 P
X G1 G1 -750 450 100 R 50 50 1 1 I
X G2 G2 -50 450 100 R 50 50 1 1 I
X S1 S1 -450 250 100 U 50 50 1 1 P
X S2 S2 250 250 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library
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update=Mi 19 Jun 2019 13:22:08 CEST
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=1
AllowBlindVias=1
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.09999999999999999
MinViaDiameter=0.45
MinViaDrill=0.2
MinMicroViaDiameter=0.3
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1
TrackWidth2=0.15
TrackWidth3=0.2
TrackWidth4=0.25
TrackWidth5=0.3
TrackWidth6=0.5
TrackWidth7=1
ViaDiameter1=0.45
ViaDrill1=0.2
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.09999999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.05
SolderMaskMinWidth=0.09999999999999999
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1
TrackWidth=0.1
ViaDiameter=0.45
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
EESchema Schematic File Version 4
LIBS:Fundamental-Board-cache
EELAYER 29 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 1 5
Title "card10 Fundamental Board Overview"
Date "2019-03-02"
Rev "0.1"
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 9000 1000 3000 1950
U 5C7CF52B
F0 "Fundamental-Board_PMIC" 50
F1 "Fundamental-Board_PMIC.sch" 50
F2 "PMIC_AMUX" I L 9000 2200 50
F3 "SDA" I L 9000 2400 50
F4 "SCL" I L 9000 2500 50
F5 "PMIC_LDO" I R 12000 1150 50
F6 "PMIC_nRST" I L 9000 2600 50
F7 "PMIC_nEN" I L 9000 2750 50
F8 "PMIC_nIRQ" I L 9000 2300 50
F9 "PMIC_PWR_HLD" I L 9000 2100 50
F10 "PMIC_GPIO" I L 9000 1950 50
F11 "1V8" I L 9000 1450 50
F12 "VSYS" I R 12000 1250 50
F13 "3V3" I L 9000 1550 50
F14 "3V3_TOP" I L 9000 1650 50
F15 "UV_LED0" I L 9000 1100 50
F16 "UV_LED1" I L 9000 1200 50
F17 "UV_LED2" I L 9000 1300 50
F18 "CHG_IN" I L 9000 1850 50
F19 "BAT+" I L 9000 1750 50
F20 "VSYS" I L 9000 2850 50
$EndSheet
$Sheet
S 9000 6450 3000 2000
U 5C7E132D
F0 "Fundamental-Board_Sensors_ECG" 50
F1 "Fundamental-Board_Sensors_ECG.sch" 50
F2 "ECG_CSB" I L 9000 7500 50
F3 "ECG_SDI" I L 9000 7600 50
F4 "ECG_SCLK" I L 9000 7800 50
F5 "ECG_SDO" I L 9000 7700 50
F6 "ECG_INT" I L 9000 7900 50
F7 "ECG_INT2" I L 9000 8000 50
F8 "ECG_FCLK" I L 9000 8200 50
F9 "ECG_AOUT" I L 9000 8300 50
F10 "1V8" I L 9000 7000 50
F11 "ECG_P" I L 9000 6550 50
F12 "ECP_N" I L 9000 6650 50
F13 "ECG_VCM" I L 9000 6750 50
$EndSheet
Text Notes 2600 3550 0 197 ~ 0
uC Section
Wire Wire Line
9000 2100 6250 2100
Wire Wire Line
6250 2200 9000 2200
Wire Wire Line
9000 2300 6250 2300
Wire Wire Line
9000 1450 7800 1450
Wire Wire Line
7800 1450 6250 1450
Text Notes 9700 2350 0 197 ~ 0
PMIC Section
Text Notes 9750 4650 0 197 ~ 0
Motion Sensor\nSection
$Sheet
S 9000 3450 3000 1400
U 5C7D379B
F0 "Fundamental-Board_Sensors_Environment" 50
F1 "Fundamental-Board_Sensors_Environment.sch" 50
F2 "1V8" I L 9000 3650 50
F3 "SDA" I L 9000 4400 50
F4 "SCL" I L 9000 4500 50
F5 "BHI160_INT" I L 9000 4100 50
F6 "BMA400_INT1" I L 9000 4200 50
F7 "BMA400_INT2" I L 9000 4300 50
$EndSheet
Wire Wire Line
7800 3650 9000 3650
Wire Wire Line
9000 4100 7500 4100
Wire Wire Line
7500 4100 7500 3400
Wire Wire Line
7500 3400 6250 3400
Wire Wire Line
6250 3500 7400 3500
Wire Wire Line
7400 3500 7400 4200
Wire Wire Line
7400 4200 9000 4200
Wire Wire Line
9000 4400 8200 4400
Wire Wire Line
7200 4400 7200 3700
Wire Wire Line
7200 3700 6250 3700
Wire Wire Line
6250 3800 7100 3800
Wire Wire Line
7100 3800 7100 4500
Wire Wire Line
7100 4500 8100 4500
Text Notes 9750 6950 0 197 ~ 0
ECG Section
Wire Wire Line
7800 7000 9000 7000
Wire Wire Line
9000 7500 7550 7500
Wire Wire Line
7550 4650 6250 4650
Wire Wire Line
9000 7600 7450 7600
Wire Wire Line
7450 4750 6250 4750
Wire Wire Line
9000 7700 7350 7700
Wire Wire Line
7350 4850 6250 4850
Wire Wire Line
9000 7800 7250 7800
Wire Wire Line
7250 4950 6250 4950
Wire Wire Line
9000 7900 7150 7900
Wire Wire Line
7150 5050 6250 5050
Wire Wire Line
7550 4650 7550 7500
Wire Wire Line
7450 4750 7450 7600
Wire Wire Line
7350 4850 7350 7700
Wire Wire Line
7250 4950 7250 7800
Wire Wire Line
7150 5050 7150 7900
Connection ~ 7800 3650
Connection ~ 7800 1450
Wire Wire Line
7800 1450 7800 3650
Connection ~ 8100 4500
Wire Wire Line
8100 4500 9000 4500
Connection ~ 8200 4400
Wire Wire Line
8200 4400 7200 4400
$Sheet
S 1050 900 5200 6350
U 5C7CF551
F0 "Fundamental-Board_uC" 50
F1 "Fundamental-Board_uC.sch" 50
F2 "PMIC_PWR_HLD" I R 6250 2100 50
F3 "SDA" I R 6250 3700 50
F4 "SCL" I R 6250 3800 50
F5 "1V8" I R 6250 1450 50
F6 "3V3" I R 6250 1550 50
F7 "3V3_TOP" I R 6250 1650 50
F8 "PMIC_AMUX" I R 6250 2200 50
F9 "PMIC_nIRQ" I R 6250 2300 50
F10 "ECG_CSB" I R 6250 4650 50
F11 "ECG_SDI" I R 6250 4750 50
F12 "ECG_SDO" I R 6250 4850 50
F13 "ECG_SCLK" I R 6250 4950 50
F14 "ECG_INT" I R 6250 5050 50
F15 "Sensor_BMA400_INT1" I R 6250 3500 50
F16 "Sensor_BHI_INT" I R 6250 3400 50
F17 "PMIC_nRST" I R 6250 2600 50
F18 "32kHz" I R 6250 6200 50
F19 "UV_LED0" I R 6250 1100 50
F20 "UV_LED1" I R 6250 1200 50
F21 "UV_LED2" I R 6250 1300 50
F22 "PMIC_nEN" I R 6250 2750 50
F23 "CHG_IN" I R 6250 1850 50
F24 "ECG_P" I R 6250 6550 50
F25 "ECG_N" I R 6250 6650 50
F26 "ECG_VCM" I R 6250 6750 50
F27 "BAT+" I R 6250 1750 50
F28 "PMIC_GPIO" I R 6250 1950 50
F29 "ECG_AOUT" I R 6250 6850 50
F30 "VSYS" I R 6250 2850 50
$EndSheet
Wire Wire Line
9000 8200 6950 8200
Wire Wire Line
6950 8200 6950 6200
Wire Wire Line
6950 6200 6250 6200
Wire Wire Line
6250 1550 9000 1550
Wire Wire Line
6250 1100 9000 1100
Wire Wire Line
9000 1200 6250 1200
Wire Wire Line
6250 1300 9000 1300
Wire Wire Line
6250 2750 9000 2750
Wire Wire Line
6250 1850 9000 1850
Wire Wire Line
6250 1750 9000 1750
Wire Wire Line
9000 6550 6250 6550
Wire Wire Line
6250 6650 9000 6650
Wire Wire Line
9000 6750 6250 6750
Wire Wire Line
6250 1950 9000 1950
Wire Wire Line
6250 1650 9000 1650
Wire Wire Line
9000 2500 8100 2500
Wire Wire Line
8100 2500 8100 4500
Wire Wire Line
9000 2400 8200 2400
Wire Wire Line
8200 2400 8200 4400
Wire Wire Line
9000 8300 6850 8300
Wire Wire Line
6850 8300 6850 6850
Wire Wire Line
6850 6850 6250 6850
Wire Wire Line
6250 2600 9000 2600
Wire Wire Line
7800 3650 7800 7000
$Comp
L Graphic:Logo_Open_Hardware_Large LOGO101
U 1 1 5D6F126A
P 1550 8400
F 0 "LOGO101" H 1550 8900 50 0001 C CNN
F 1 "Logo_Open_Hardware_Large" H 1550 8000 50 0001 C CNN
F 2 "Symbol:OSHW-Logo2_7.3x6mm_SilkScreen" H 1550 8400 50 0001 C CNN
F 3 "~" H 1550 8400 50 0001 C CNN
1 1550 8400
1 0 0 -1
$EndComp
$Comp
L Mechanical:Fiducial FID101
U 1 1 5F3EEBF0
P 2700 8450
F 0 "FID101" H 2785 8496 50 0000 L CNN
F 1 "Fiducial" H 2785 8405 50 0000 L CNN
F 2 "Fiducial:Fiducial_0.75mm_Mask1.5mm" H 2700 8450 50 0001 C CNN
F 3 "~" H 2700 8450 50 0001 C CNN
1 2700 8450
1 0 0 -1
$EndComp
$Comp
L Mechanical:Fiducial FID103
U 1 1 5F3EF61C
P 3200 8450
F 0 "FID103" H 3285 8496 50 0000 L CNN
F 1 "Fiducial" H 3285 8405 50 0000 L CNN
F 2 "Fiducial:Fiducial_0.75mm_Mask1.5mm" H 3200 8450 50 0001 C CNN
F 3 "~" H 3200 8450 50 0001 C CNN
1 3200 8450
1 0 0 -1
$EndComp
$Comp
L Mechanical:Fiducial FID105
U 1 1 5F3EF903
P 3700 8450
F 0 "FID105" H 3785 8496 50 0000 L CNN
F 1 "Fiducial" H 3785 8405 50 0000 L CNN
F 2 "Fiducial:Fiducial_0.75mm_Mask1.5mm" H 3700 8450 50 0001 C CNN
F 3 "~" H 3700 8450 50 0001 C CNN
1 3700 8450
1 0 0 -1
$EndComp
$Comp
L Mechanical:Fiducial FID106